Version Found: MIG 7 Series v1.7.a
Version Resolved: See (Xilinx Answer 45195)
MIG 7 Series fails in Vivado GUI mode when the MIG design signals are enabled.
This is a result of the ChipScope cores being inferred as black boxes, and the following error message can be seen:
This includes MIG example designs created by using the "Open IP Example Design" option in the Vivado GUI.
To work around this issue, use the vivado.tcl script generated by MIG and located in the /example_design/par/ and /user_design/par/ directories.
vivado -source vivado.tcl -mode batch
10/16/2012 - Initial release