2. 技术支持
  3. AR# 52264: Does Vivado Synthesis support Asymmetric read/write port width block RAM inference?

AR# 52264

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Does Vivado Synthesis support Asymmetric read/write port width block RAM inference?

描述

Does Vivado Synthesis support Asymmetric read/write port width block RAM inference?

解决方案

Starting with 2014.1, Asymmetric read/write port with block RAM inference feature is supported in Vivado Synthesis by default.

In 2013.3 and 2013.4 versions, this is also supported but you must use the following TCL parameter to enable this feature.

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter supportAsymRam true"

Prior to 2013.3, Vivado Synthesis did not support Asymmetric read/write port width block RAM inference.


链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
57854 2014.1 Vivado Synthesis - Some patterns of asymmetric BRAM inference are not successful. N/A N/A
AR# 52264
日期 04/16/2014
状态 Active
Type 已知问题
Tools
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