We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52655

Kintex-7 Connectivity Kit, Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform


The 7 Series Integrated Block for PCI Express core does not link up successfully on an Intel Z77 (Ivy Bridge) platform. This affects the out-of-box experience for customers wishing to use the Kintex-7 Connectivity TRD (pre v1.4 of the TRD).


This is a known issue for the core implemented in Artix and Kintex devices due to an Intel errata. To work around this issue, please refer to (Xilinx Answer 51135).

An out-of-the-box solution is available to enable customers to run the Kintex-7 Connectivity TRD. This involves using a particular set of files (bit and MCS file) when running the Connectivity TRD. The files needed, k7_conn_trd.bit and kc705_conn_trd.mcs, can be found below.

For information on how to run the Connectivity TRD, please refer to the Kintex-7 FPGA Connectivity Targeted Reference Design User Guide (UG927):

This solution is no longer required for Connectivity TRD (v1.4); the PCIe IP has been updated, so this patch no longer applies.


文件名 文件大小 File Type
k7_conn_trd.bit 8 MB BIT
kc705_conn_trd.mcs 23 MB MCS



Answer Number 问答标题 问题版本 已解决问题的版本
50555 Kintex-7 FPGA Connectivity Kit and Targeted Reference Design - Release Notes and Known Issues Master Answer Record N/A N/A
AR# 52655
日期 06/05/2013
状态 Active
Type 综合文章
Boards & Kits
  • Kintex-7 FPGA Connectivity Kit