In Spartan-6 devices, it is required that the IDELAY_VALUE for PCI core is set to 83. However, even though the IDELAY_VALUE is set in the UCF, the tool does not apply them because the IODELAY is inferred rather than instantiated.
To work around this issue, perform the following steps:
- Implement the design as usual. Let it finish and at the end it should generate an NCD file (the <design_name>.ncd from PAR).
- Launch FPGA Editor tool and load the <design_name>.ncd file and the <design_name>.pcf
- In the Name Filter, search for *IODELAY*; there should be 36 of them for the PCI core if the design contains other IODELAY for other purposes, you can do search *<core_name>*IODELAY* (replace <core_name> with the name of the PCI module in the design) and that will return the ones just for the PCI core.
- Click on the "editmode" button once.
- Click on each one of the IODELAY block from the search result you get in step 3 above, and then click the editblock button.
Note: If the editblock window shows with light gray background, please close this window, and re-do step 4 above until the editblock window shows solid black background. Otherwise it is not editable.
- In the editblock window. Click on the "F=" button along the toolbar within this window; this will show the attributes for this block.
Perform steps 5 and 6 again until all the IODELAY blocks have been changed. Then click save on FPGA editor.
- Change the IDELAY_VALUE in the attribute section to 83.
- Change the IDELAY_TYPE checkbox to FIXE
Once done, click the Save button (second button from the right along the toolbar within the window) to save and close the window.
11/12/2012 - Initial release