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AR# 53430

2012.4 Timing - Artix-7 Base Targeted Reference Design has setup violations


I run the Artix-7 FPGA Base Targeted Reference design in Vivado Design Suite and I get 10 paths with setup violations, with TSN of -0.478 ns and a pulsewidth violation of WPWS of -0.034 ns. When I investigated further, I noticed that the total delay for the worst path, it was 95% routing. How can I fix this issue?


You can try setting the router effort level to high.

This issue is scheduled to be fixed in the next major release of the software.

AR# 53430
日期 12/12/2012
状态 Active
Type 已知问题