Error: (vsim-7) Failed to open VHDL file "sc_sequ_cthread.hdltvin.dat" in rb mode.
In Vivado HLS, click on the Co-Simulation icon and check Verilog or VHDL for RTL selection.
Optionally, select "Setup Only" to just generate the files.
Click OK to generate the files.
The scripts and wrappers will be generated and placed in the project's solution/sim/verilog (or vhdl) folder.
To run simulation with Modelsim, source the run_modelsim.sh or .bat file depending on your OS.
AR# 53513 | |
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日期 | 07/10/2014 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools |