AR# 53701

描述

Version Found: 3.92
Version Resolved: See (Xilinx Answer 50642)

The MIG Virtex-6 DDR2 design uses the parameter DDR2_EARLY_CS to advance CS by 1 cycle in UDIMM designs. 

However the rtl incorrectly enables the early CS advancement for component designs when the CK_WIDTH<5 and the DQ_WIDTH>=64. 

This occurs for example in a 64-bit DDR2 interface using four x16 components.

Failures have been seen in hardware as read leveling calibration failures where the pattern read back during read leveling stage 1 is incorrect. 

Scope measurements show the 1 cycle early assertion of CS compared to the rest of the DDR2 commands.

解决方案

DDR2_EARLY_CS is assigned as follows in the example_design/rtl/phy/phy_top.v/.vhd or user_design/rtl/phy/phy_top.v/.vhd files:

  localparam DDR2_EARLY_CS = ((CLK_PERIOD < 10000) & ( DQ_WIDTH >= 64) &
                             (CK_WIDTH < 5) & (DRAM_TYPE == "DDR2") &
                             (REG_CTRL == "OFF"));

To work around this issue, the parameter assignment should be changed to:

  localparam DDR2_EARLY_CS = ((CLK_PERIOD < 10000) & ( DQ_WIDTH >= 64) &
                             (CK_WIDTH < 4) & (DRAM_TYPE == "DDR2") &
                             (REG_CTRL == "OFF"));