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  3. AR# 54025: MIG 7 Series - IP Release Notes and Known Issues for Vivado

AR# 54025

MIG 7 Series - IP Release Notes and Known Issues for Vivado

描述

This answer record contains the Release Notes and Known Issues for the MIG 7 Series Core and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

MIG IP Page:

https://www.xilinx.com/products/intellectual-property/MIG.htm

解决方案

General Information

Supported devices can be found in the following locations:

Note: For a complete part and package support list, open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core Version Vivado Tools
Version
v4.0 rev42017.2
v4.0 rev32017.1
v4.0 rev22016.4
v4.0 rev12016.3
v4.02016.2
v3.02016.1
v2.4 rev12015.4
v2.42015.3
v2.3 Rev22015.2
v2.3 Rev12015.1
v2.32014.4
v2.22014.3
v2.12014.2
v2.0 Rev32014.1
v2.0 Rev22013.4
v2.0 Rev12013.3
v2.02013.2
v1.9a2013.1
v1.8a2012.4
v1.7a2012.3
v1.62012.2
v1.52012.1


For a list of supported memory interfaces and features for 7 Series FPGAs, see the 7 Series FPGAs Memory Interface Solution Data Sheet (DS176) and 7 Series FPGAs Memory Interface Solution User Guide (UG586) located at:

https://www.xilinx.com/cgi-bin/docs/ipdoc?c=mig_7series;v=latest;d=ug586_7Series_MIS.pdf


For a list of supported frequencies for 7 Series FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the Documentation Centre 

The MIG tool includes the appropriate frequency range for each specific memory interface configuration

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Table 2 provides answer records for general guidance when using the MIG 7 Series core.

Table 2: General Guidance

Answer RecordTitle
(Xilinx Answer 34243)Xilinx MIG Solution Center
(Xilinx Answer 43879)7 Series MIG DDR3 - Hardware Debug Guide
(Xilinx Answer 33566)Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
(Xilinx Answer 42944)Design Advisory Master Answer Record for Virtex-7 FPGA
(Xilinx Answer 42946)Design Advisory Master Answer Record for Kintex-7 FPGA
(Xilinx Answer 51456)Design Advisory Master Answer Record for Artix-7 FPGA
(Xilinx Answer 42665)MIG 7 Series - Why does the MIG Example Design fail in BitGen?
(Xilinx Answer 42036)MIG 7 Series - Internal/External Vref Guidelines
(Xilinx Answer 40603)MIG 7 Series DDR3/DDR2 - Clocking Guidelines
(Xilinx Answer 58057)MIG 7 Series - IES and VCS simulator support
(Xilinx Answer 66422)

MIG 7 Series - Debug Signals are not available when using IP Integrator


Table 3: List of Memory Devices Supported

ComponentsRDIMMsUDIMMsSODIMMs
DDR3 SDRAMMT41J128M8XX-125MT9JSF25672PZ-1G6MT9JSF25672AZ-1G9MT8JTF12864HZ-1G6
MT41J128M8XX-15EMT9JSF25672PZ-1G4MT9JSF25672AZ-1G6MT8JSF12864HZ-1G4
MT41J64M16XX-125GMT9KSF51272PZ-1G6MT9JSF25672AZ-1G1MT8JTF25664HZ-1G4
MT41J64M16XX-125MT9KSF51272PZ-1G4MT8JTF51264AZ-1G6MT8JSF25664HZ-1G1
MT41J64M16XX-15ET9KSF25672PZ-1G4MT8JTF51264AZ-1G4MT8KTF51264HZ-1G9
MT41J256M8XX-107MT18JSF25672PDZ-1G6MT8JTF12864AZ-1G6MT8KTF51264HZ-1G6
MT41J256M8XX-125MT18JSF51272PDZ-1G4MT8JTF12864AZ-1G4MT4KTF25664HZ-1G9
MT41J256M8XX-15EMT18JSF51272PDZ-1G6MT8JTF25664AZ-1G4MT8KTF25664HZ-1G6
MT41J256M8XX-187EMT18KSF1G72PDZ-1G6MT8KTF51264AZ-1G6MT8KSF25664HZ-1G4
MT41J128M16XX-107GMT18KSF1G72PDZ-1G4MT8KTF51264AZ-1G4MT8KTF25664HZ-1G4
MT41J128M16XX-107MT8KTF25664AZ-1G4MT8KTF12864HZ-1G9
MT41J128M16XX-125MT8KTF25664AZ-1G6MT9KSF51272HZ-1G6
MT41J128M16XX-15EMT9KSF25672AZ-1G6MT16JTF25664HZ-1G6
MT41J128M16XX-187EMT9KSF25672AZ-1G4MT16JTF25664HZ-1G4
MT41J512M8XX-107MT16JTF51264AZ-1G4MT16JTF1G64HZ-1G4
MT41J512M8XX-125MT16KTF51264AZ-1G4MT16JTF51264HZ-1G4
MT41J512M8XX-15EMT16KTF51264AZ-1G6MT8JSF25664HDZ-1G4
MT41J256m16XX-107MT18JSF25672AZ-1G4MT16KTF51264HZ-1G4
MT41J256m16XX-125MT18JSF51272AZ-1G6MT16KSF51264HZ-1G4
MT41J256m16XX-15EMT18KSF51272AZ-1G4MT16KTF51264HZ-1G6
MT18KSF1G72HZ-1G6
MT18KSF51272HZ-1G4
MT16KTF1G64HZ-1G6
DDR3L SDRAMMT41K64M16XX-107
MT9KSF51272PZ-1G6MT8KTF51264AZ-1G6MT8KTF51264HZ-1G9
MT41K64M16XX-125
MT9KSF51272PZ-1G4MT8KTF51264AZ-1G4MT8KTF51264HZ-1G6
MT41K64M16XX-15E
MT9KSF25672PZ-1G4MT8KTF25664AZ-1G4MT4KTF25664HZ-1G9
MT41K256M8XX-125
MT18KSF1G72PDZ-1G6MT8KTF25664AZ-1G6MT8KTF25664HZ-1G6
MT41K256M8XX-15E
MT18KSF1G72PDZ-1G4MT9KSF25672AZ-1G6MT8KSF25664HZ-1G4
MT41K128M16XX-15E
MT9KSF25672AZ-1G4MT8KTF25664HZ-1G4
MT41K512M8XX-107
MT16KTF51264AZ-1G4MT8KTF12864HZ-1G9
MT41K512M8XX-125
MT16KTF51264AZ-1G6MT9KSF51272HZ-1G6
MT41K512M8XX-15E
MT18KSF51272AZ-1G4MT16KTF51264HZ-1G4
MT41K256M16XX-107
MT16KSF51264HZ-1G4
MT41K256M16XX-125
MT16KTF51264HZ-1G6
MT41K256M16XX-15E
MT18KSF1G72HZ-1G6
MT41K512M8THD-15E
MT18KSF51272HZ-1G4
MT41K256M32SLD-125MT16KTF1G64HZ-1G6
MT41K1G8TRF-107
MT41K1G8TRF-125
DDR2 SDRAMMT47H128M16XX-25EMT9HTF12872PZ-80EMT8HTF12864AZ-800MT8HTF12864HZ-800
MT47H128M8XX-25/25EMT9HTF12872PZ-667MT8HTF25664AZ-800MT8HTF25664HZ-800
MT47H256M8XX-25EMT9HTF12872AZ-80E
MT47H64M16XX-25/25E
MT47H512M8WTR-25E/25E L
MT47H64M16HR-25E
QDRII+ SRAMK7S3236T4C-FC45
K7S3218T4C-FC45
CY7C15632KV18-500BZC
CY7C1565KV18-500BZC
CY7C25632KV18-500BZC
CY7C2565KV18-500BZC
CY7C2263KV18-550BZXI
CY7C2265KV18-550BZC
CY7C2163KV18-550BZXI
CY7C2165KV18-550BZC
CY7C25632KV18-450BZC
CY7C2565KV18-450BZC
CY7C25442KV18-333BZI*
CY7C2264XV18-450BZXC*
CY7C2262XV18-450BZXC*
CY7C2564XV18-450BZXC*
CY7C2562XV18-450BZXC*
CY7C2563KV18-500BZC/450BZC
CY7C25652KV18-500BZC/450BZC
CY7C2665KV18-550BZXC/450BZXI
CY7C2663KV18-550BZXC/450BZXI
RLDRAM IIMT49H16M36XX-18/25E/25/33
MT49H32M18XX-18/25E/25/33
MT49H8M36XX-25/33
MT49H16M18XX-25/33
RLDRAM IIIMT44K16M36XX-125
MT44K16M36XX-125E/125
MT44K32M18XX-125
MT44K32M18XX-125E
MT44K32M36XX-125
MT44K32M36XX-125E
LPDDR2MT42L128M16D1KL-25-IT/3-IT
MT42L64M32D1KL-25-IT/3-IT
MT42L256M16D1LG-25-WT
MT42L128M32D1LG-25-WT


*Components for Burst Length 2

Known and Resolved Issues

The following table provides known issues for the MIG 7 Series core, starting with v1.9a, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 4: MIG 7 Series DDR3/DDR2 SDRAM

The following table provides known issues for MIG 7 series DDR3/DDR2 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 69313)MIG 7 Series - Notification when Modifying Default MIG Parameters for Artix-7 or Spartan-7 Devices with DDR3, DDR3L, or LPDDR2 Interfaces 4.0 rev3N/A
(Xilinx Answer 67179)MIG 7 Series - Memory clock period range is updated in Vivado 2016.2 and may cause errors during IP upgradeN/AN/A
(Xilinx Answer 67520)MIG 7 Series DDR3 - Periodic reads used for VT tracking may be missing during continuous write transactions 1.94.0 rev1
(Xilinx Answer 67168)MIG 7 Series - IP GUI crashes when clicking "browse" button on Windows 8 or Windows 10
3.04.0 rev1
(Xilinx Answer 66969)MIG 7 Series - Can not select 72-bit data width in the MIG wizard GUI  when the part is XC7Z035FFG676-2 2.4 rev14.0 rev1
(Xilinx Answer 58621)
MIG 7 Series - Critical warnings occur when multiple MIG IP are added to the same project
2.0 Rev1Not Resolved
(Xilinx Answer 60050)MIG 7 Series DDR3/DDR2 - cmp_data_r and dbg_rddata_r are not aligned2.0Not Resolved
(Xilinx Answer 60952)MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers2.0Not Resolved
(Xilinx Answer 65386)MIG 7 Series - FATAL error seen during simulation of MIG example design 2.3 Rev2N/A
(Xilinx Answer 65355)
MIG 7 Series - IP OOC synthesis run goes out-of-date when "Validate Design" is run on the block design
2.3 Rev2N/A
(Xilinx Answer 63122)
MIG 7 Series DDR2/DDR3 v2.3 - Automated and manual write window margin check feature is not available on example design
2.3
N/A
(Xilinx Answer 63640)MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen2.3N/A
(Xilinx Answer 63493)MIG 7 Series - Errors when regenerating a remotely sourced MIG core in customers larger design 2.3N/A
(Xilinx Answer 63393)MIG 7 Series - Crashes when Read XDC/UCF option is used in Windows 8.1 2.3N/A
(Xilinx Answer 63178)MIG 7 Series - DDR3 - Glitches seen on address/command bus in simulation with 2:1 controller2.3N/A
(Xilinx Answer 63227)MIG 7 Series - No buffer option always expects 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz2.3N/A
(Xilinx Answer 62813)MIG 7 Series - Multi-controller designs require custom part to be created for each controller 2.3N/A
(Xilinx Answer 62368)Design Advisory for MIG 7 Series DDR3 - Calibration updates in MIG 7 Series v2.3 available with Vivado 2014.4 provide additional write margin2.3N/A
(Xilinx Answer 63463)MIG 7 Series DDR3 - Calibration updates to improve read and write margin result in an increase in calibration time starting with MIG v2.1 released with Vivado 2014.2. Is there a way to reduce the calibration time?2.2N/A
(Xilinx Answer 62615)MIG 7 Series DDR3 (IPI flow ONLY) - Warning message generated upon IPI Upgrade - Clocking structure for MIG has been updated2.2N/A
(Xilinx Answer 61916)MIG 7 Series AXI DDR3/DDR2 Enabling Narrow Burst option within MIG does not affect the RTL and the parameter remains set to '0'2.2N/A
(Xilinx Answer 62161)MIG 7 Series - Errors that do not mean anything to the user are flagged when trying to customize the MIG core2.1N/A
(Xilinx Answer 61790)MIG 7 Series - DDR3 - app_rd_data_end stays high2.1N/A
(Xilinx Answer 61705)MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported2.1N/A
(Xilinx Answer 59167)Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces2.1N/A
(Xilinx Answer 60687)MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1 released with Vivado 2014.2 that provide additional read margin for data rates above 1333Mbps 2.1N/A
(Xilinx Answer 59913)MIG 7 Series DDR3 - Traffic Generator detects false error messages when VIOs are used to change the data modes2.0N/A
(Xilinx Answer 55040)MIG 7 Series - DDR3, LPDDR2, and DDR2 support changes for Virtex-7 HT devices1.9aN/A
(Xilinx Answer 54584)MIG 7 Series - Needed XDC constraint changes when using a Synplify netlist within Vivado1.8aN/A
(Xilinx Answer 56231)MIG 7 Series DDR3/2 - In some instances, the MIG default pin-out will assign an empty address/ctrl byte group1.6N/A
(Xilinx Answer 52176)MIG 7 Series DDR3 - 48-bit design unable to fit into 2 HP banks1.6N/A
(Xilinx Answer 66892)MIG 7 Series - DDR3 Custom part simulation may fail with undefined variable:TDQSCK_DLLDIS2.43.0
(Xilinx Answer 66788)Design Advisories for MIG 7 Series -DDR3 DQS_BIAS is not properly enabled for HR banks causing potential calibration failures.2.33.0
(Xilinx Answer 65351)MIG 7 series - GUI shows incorrect tested Vivado version number2.3 Rev2v2.4
(Xilinx Answer 66181) MIG 7 Series DDR3 - IBUF_LOW_PWR may be incorrectly enabled in Vivado 2015.1 and 2015.2
2.3 Rev1v2.4
(Xilinx Answer 63775)MIG 7 Series DDR2/DDR3 v2.3 - Maximum speed for dual rank/twin die DDR3 is updated 2.32.3 Rev1
(Xilinx Answer 63165)MIG 7 Series DDR2/DDR3 v2.2/2.3- Additional BUFG being added in "opt_design" on the "freq_refclk" can lead to minimum pulse width timing violations2.32.3 Rev1
(Xilinx Answer 60527)MIG 7 Series - Virtex-7 HT - Error is generated when trying to open MIG 7 Series tool when targeting a part with an flg package - Failed to generate custom UI outputs2.0 Rev32.3 Rev1
(Xilinx Answer 59284)MIG 7 Series DDR3/DDR2 - Manual Window Check feature does not work with VIO 2.02.02.3 Rev1
(Xilinx Answer 62891)MIG 7 Series - DDR3 - 72-bit AXI4 interface generated with ECC disabled2.2v2.3
(Xilinx Answer 62852)MIG 7 series - GUI restricts to select required Clock Period that was allowed in earlier MIG versions 2.2v2.3
(Xilinx Answer 62204)MIG 7 series - IPI Design Create Clock Constraint Critical Warning -Constraints 18-1056 Clock 'sys_clk' completely overrides clock 'sys_diff_clock_clk_p' 2.1v2.3
(Xilinx Answer 62160)
MIG 7 series - Is Dynamic ODT supported?2.1v2.3
(Xilinx Answer 60995)MIG 7 Series - UG586 - Incorrect CKE_ODT_BYTE_MAP, CKE_MAP and ODT_MAP attributes2.0 Rev3v2.3
(Xilinx Answer 60993)MIG 7 Series DDR3 - "Memory Details" in GUI does not correctly compute density for TwinDie custom parts2.0 Rev3v2.3
(Xilinx Answer 60822)MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader"2.0 Rev3v2.3
(Xilinx Answer 60847)MIG 7 Series Multi-Controller - For designs with the Reference Clock set to "Use System Clock", the rtl has ref_clk connected to the last controller's input clock regardless of which controller input clock is set to 200MHz 2.1v2.3
(Xilinx Answer 60846)MIG 7 Series DDR3 - Kintex-7 -2L/-3L - Incorrect refclk frequency of 400MHz generated for designs operating above 1333 Mbps (667MHz) causes DRC error during implementation
2.1v2.3
(Xilinx Answer 61744)MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2. Errors were not seen in previous versions. 2.1v2.2
(Xilinx Answer 61521)MIG 7 Series - cannot generate data width greater than 8-bits for CPG325 packages2.1v2.2
(Xilinx Answer 61576)MIG 7 Series DDR3 - After re-customization, ECC will become "Disabled" even though it was originally "Enabled"2.1v2.2
(Xilinx Answer 61356)MIG 7 Series - Artix-7 CSG235 only contains HR banks but the MIG Bank Selection page shows Bank 34 as HP2.1v2.2
(Xilinx Answer 60990)MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts2.0 Rev3v2.2
(Xilinx Answer 60988)MIG 7 Series DDR3/DDR2 - Examples for ADDR_MAP and CK_BYTE_MAP are incorrect2.0 Rev3v2.2
(Xilinx Answer 60958)MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks2.0 Rev3v2.2
(Xilinx Answer 60480)MIG 7 Series - Receiving ERROR: [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used2.0 Rev2v2.2
(Xilinx Answer 60051)MIG 7 Series DDR3 - VCS simulations fail with unresolved modules2.0 Rev3v2.2
(Xilinx Answer 58667)MIG 7 Series - Out of Context (OOC) flow fails during synthesis when sys_clk is specified as "No Buffer" in the MIG 7 Series core generation.v1.9v2.2
(Xilinx Answer 60000)MIG 7 Series - Artix-7 - MIG 7 Series will not open for xq7a200t devices2.0 Rev3v2.1
(Xilinx Answer 59517)MIG 7 Series - Running example design produces [Constraints 18-402] warnings due to invalid start points2.0 Rev2v2.1
(Xilinx Answer 58634)MIG 7 Series - All VHDL designs fail VCS simulations2.0 Rev1v2.1
(Xilinx Answer 57782)MIG 7 Series DDR3 - issues with sys_clk type in ZC706 reference design2.0 Rev1v2.1
(Xilinx Answer 59632)MIG 7 Series - support for Artix XC7A35T and XC7A50T devices is missing in 2013.42.0 Rev22.0 Rev3
(Xilinx Answer 59714)MIG 7 Series - customization of MIG core in Vivado removes and fails to regenerate some files2.0 Rev22.0 Rev3
(Xilinx Answer 59515)MIG 7 Series - Vivado does not generate the correct VHDL instantiation template2.0 Rev22.0 Rev3
(Xilinx Answer 59606)MIG 7 Series DDR3 - Simulation fails in Vivado Simulator with ERROR: [VRFC 10-51] string is an unknown type2.0 Rev22.0 Rev3
(Xilinx Answer 58647)MIG 7 Series DDR3 - Unable to derive 150MHz input clock frequency2.0 Rev22.0 Rev3
(Xilinx Answer 58894)MIG 7 Series DDR3 - IP generation error message occurs for 8Gb part2.0 Rev22.0 Rev 3
(Xilinx Answer 58668)MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado GUI. Stand-alone support is not available even though scripts are provided. 2.0 Rev2
2.0 Rev 3
(Xilinx Answer 58666)MIG 7 Series DDR3/DDR2 - MIG GUI allows higher value (400MHz) than the DS191 specification (333Mhz/667 Mbps) for Kintex-7 FBG in -1 for DDR3L (1.35V IO) 2.0 Rev 12.0 Rev 3
(Xilinx Answer 57221)MIG 7 Series DDR3 RDIMM - non-ideal setting for RC3/4/5 for DRAM loads of 8 or more2.02.0 Rev 3
(Xilinx Answer 56387)MIG 7 Series - Timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains2.02.0 Rev 3
(Xilinx Answer 57037)MIG 7 Series - Vivado DCP flow not supported for MIG IP2.0 Rev12.0 Rev2
(Xilinx Answer 58172)MIG 7 Series DDR3/DDR2 - MIG includes incorrect maximum frequencies for 2:1 (half-rate) DDR3/DDR2 controller designs targeting -2 and -1 speed grades. Maximum spec numbers in datasheets are correct.2.0 Rev12.0 Rev2
(Xilinx Answer 58855)MIG 7 Series DDR3/DDR2 - The AXI address width is incorrect if MIG is generated in an IPI block diagram2.02.0 Rev2
(Xilinx Answer 57657)MIG 7 Series - mig.prj created in XPS is not read correctly in Vivado2.02.0 Rev1
(Xilinx Answer 56385)MIG 7 Series DDR3 - Timing failures can occur with larger SSI devices2.02.0 Rev1
(Xilinx Answer 57662)MIG 7 Series AXI - ECC Enabled - 4:1 - dbg_rddata_r is half the width of dbg_rddata2.02.0 Rev1
(Xilinx Answer 57279)MIG 7 Series DDR3 RDIMM - Clock Driver Enable settings for RC1 may cause initialization failures2.02.0 Rev1
(Xilinx Answer 57338)MIG 7 Series DDR3 - VHDL ONLY - Designs fail during write calibration when the pin-out has a bank containing Addr/Cont groups in T0, T1, and T2 and a Data group in T31.92.0 Rev1
(Xilinx Answer 55015)MIG 7 Series DDR3 - dbg_dqs VIO selection is not connected to mux_rd_rise/fall signals in debug cores 1.8a2.0 Rev1
(Xilinx Answer 54710)MIG 7 Series - DDR3 - Controller hangs on a read-modify-write operation1.8.a2.0 Rev1
(Xilinx Answer 57758)MIG 7 Series DDR3/DDR2 - Vivado implementation places PLL to MMCM clock "pll_clk3" on backbone route preventing a "sys_clk" driven from a different bank from using the required route1.7a2.0 Rev1
(Xilinx Answer 54918)MIG 7 Series DDR3 - ChipScope Debug Signal connections for OCLKDELAY calibration are out of date after installing patch from Answer Record 53420 1.7a2.0 Rev1
(Xilinx Answer 57436)MIG 7 Series DDR3 - Single rank DDR3 RDIMMs incorrectly include one Chip Select (CS_n) pin when two are required. The design therefore does not program the SPD register. 1.72.0 Rev1
(Xilinx Answer 55531)Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied1.9.a2.0
(Xilinx Answer 55165)MIG 7 Series DDR3, Vivado Implementation - Improper high utilization of the MIG core is seen due to signal replication from MAX_FANOUT attributes. Timing violations may also be seen on signals with MAX_FANOUT attributes 1.9.a2.0
(Xilinx Answer 55192)MIG 7 Series - Using ChipScope in Vivado1.9.a2.0
(Xilinx Answer 58307)MIG 7series - IPI block design Interrupt signal direction is incorrect1.92.0
(Xilinx Answer 55013)MIG 7 Series DDR3 - The MIG 7 Series tool does not allow selecting 800 MHz for dual rank DIMMs in a -2 FPGA design when a 1.35V/1,5V part is selected using the 1.5V option1.8.a2.0
(Xilinx Answer 55011)MIG 7 Series DDR3 - PRBS Read Leveling Debug signals are not connected to dbg_dqs VIO control 1.8a2.0
(Xilinx Answer 53433)MIG 7 Series DDR3/DDR2 - MAX_FANOUT attribute not being honored1.8.a2.0
(Xilinx Answer 53435)MIG 7 Series DDR3/DDR2 - Timing violations may be seen in 2:1 designs running around 533 MHz within u_ddr_mc_phy1.8.a2.0
(Xilinx Answer 54384)MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected1.8.a2.0
(Xilinx Answer 55056)MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts1.8.a2.0
(Xilinx Answer 55060)MIG 7 Series DDR3/DDR2 - AXI Interface Enabled - Controller services write command before read is completed.1.8.a2.0
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.52.0

 

Table 5: MIG 7 Series LPDDR2

 

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69313)MIG 7 Series - Notification when Modifying Default MIG Parameters for Artix-7 or Spartan-7 Devices with DDR3, DDR3L, or LPDDR2 Interfaces 4.0 rev3N/A
(Xilinx Answer 66140)MIG 7 Series - LPDDR2 - Incorrect width of app_wdf_mask signal seen in instantiation template and MIG top level file mig_7series_0.v 2.4 Rev13.0
(Xilinx Answer 63853)MIG 7 Series - LPDDR2 - Incorrect MAX data rate for -1Q Artix parts2.22.3
(Xilinx Answer 63859)MIG 7 Series - LPDDR2 - Simulation errors seen when simulation a MIG design 2.12.3 Rev1
(Xilinx Answer 63854)MIG 7 Series - LPDDR2 - Some of the Micron part names do not match with the Micron Website2.22.3 Rev1
(Xilinx Answer 63640)MIG 7 Series - User must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen2.3

N/A

(Xilinx Answer 63227)MIG 7 Series - No buffer option always expects 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz2.32.3 Rev1
(Xilinx Answer 61705)MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported2.1N/A
(Xilinx Answer 60822)MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader"2.0 Rev32.3
(Xilinx Answer 58621)MIG 7 Series - CRITICAL WARNING message when multiple MIG IP are added to the same project2.0 Rev1Not Resolved
(Xilinx Answer 60952)MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers2.0Not Resolved
(Xilinx Answer 61805)MIG 7 Series - LPDDR2 calibration fails in Phase Detection when memory operating frequency is 200MHZ2.12.3 Rev1
(Xilinx Answer 61521)MIG 7 Series - Cannot generate data width greater than 8-bits for CPG325 packages2.1v2.2
(Xilinx Answer 60990)MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts2.0 Rev3v2.2
(Xilinx Answer 60958)MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks2.0 Rev3v2.2
(Xilinx Answer 60480)MIG 7 Series - Receiving ERROR: [ Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used2.0 Rev2 v2.2
(Xilinx Answer 60166)MIG 7 Series - LPDDR2 - [Route 35-54] Net: < net_name> is not completely routed2.0 Rev2 2.1
(Xilinx Answer 59517)MIG 7 Series - Running example design produces [Constrains 18-402] warnings due to invalid startpoints2.0 Rev2 2.1
(Xilinx Answer 58634)MIG 7 Series - All VHDL designs fail VCS simulations2.0 Rev12.1
(Xilinx Answer 59632)MIG 7 Series - support for Artix XC7A35T and XC7A50T devices is missing in 2013.42.0 Rev2 2.0 Rev3
(Xilinx Answer 59714)MIG 7 Series - recustomization of MIG core in Vivado removes and fails to regenerate some files2.0 Rev2 2.0 Rev3
(Xilinx Answer 59515)MIG 7 Series - Vivado does not generate the correct VHDL instantiation template2.0 Rev2 2.0 Rev3
(Xilinx Answer 58668)MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado GUI. Stand-alone support is not available even though scripts are provided. 2.0 Rev2 2.0 Rev3
(Xilinx Answer 56387)MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains2.02.0 Rev3
(Xilinx Answer 57037)MIG 7 Series - Vivado DCP flow not supported for MIG IP2.0 Rev12.0 Rev2
(Xilinx Answer 55536)Design Advisory for MIG 7 Series LPDDR2 - MIG allows incorrect placement of CK/CK# pairs when using the "Verify Pin Changes and Update Design" and "Fixed Pin-Out" flows. Documentation and "New Design" flow are correct.1.9 a2.0

 


Table 6: MIG 7 Series QDRII+ SRAM

The following table provides known issues for MIG 7 series QDRII+ SRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 65606)MIG 7 Series QDRII+, RLDRAM2, RLDRAM3 - false error message for allocation on Vref site2.4v3.0
(Xilinx Answer 65414)Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin 2.3v2.4
(Xilinx Answer 63640)MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen2.3N/A
(Xilinx Answer 63227)MIG 7 Series - No buffer option always expects 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz2.3v2.3 Rev1
(Xilinx Answer 60990)MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts2.0 Rev3v2.2
(Xilinx Answer 60958)MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks2.0 Rev3v2.2
(Xilinx Answer 60868)MIG 7 Series - QDRII+ - invalid clock period warning2.0 Rev3v2.1
(Xilinx Answer 60822)MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader"2.0 Rev3v2.2
(Xilinx Answer 60480)MIG 7 Series - Receiving ERROR: [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used2.0 Rev2v2.22.2
(Xilinx Answer 60346)MIG 7 Series QDRII+ - fails to prevent 2 CQ/CQ# pairs from being placed in the same bank2.0 Rev2v2.1
(Xilinx Answer 59517)MIG 7 Series - Running example design [Constraints 18-402] warnings due to invalid startpoints2.0 Rev2v2.1
(Xilinx Answer 58668)MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado GUI. Stand-alone support is not available even though scripts are provided.2.0 Rev2v2.12.1
(Xilinx Answer 58634)MIG 7 Series - All VHDL designs fail VCS simulations2.0 Rev1N/A
(Xilinx Answer 58621)MIG 7 Series - CRITICAL WARNING message when multiple MIG IP are added to the same project2.0 Rev1N/A
(Xilinx Answer 60952)MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers2.0 N/A
(Xilinx Answer 56387)MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains2.0 v2.0 Rev3
(Xilinx Answer 54338)MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection1.8.aNever Fix
(Xilinx Answer 57760)MIG 7 Series QDRII+ - Stage 1 calibration will always pass even if no edges are detected1.6N/A
(Xilinx Answer 61705)MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported2.1N/A
(Xilinx Answer 57437)MIG 7 Series QDRII+ - SIM_BYPASS_INIT_CAL="SKIP" is not supported for simulations2.0 N/A
(Xilinx Answer 55129)MIG 7 Series+ - Cypress memory model fails simulation for designs with Burst Length{BL} = 2 and Data Width = 181.5N/A
(Xilinx Answer 62322)MIG 7 Series QDR/RLD memory debug signals don't show bit wise assignment on Vivado 2013.32014.32014.4
(Xilinx Answer 60126)MIG 7 Series QDRII+ - Verify Pin Out fails to verify CK placement rule for QDRII+ SRAM designs2.0 Rev3v2.1
(Xilinx Answer 59632)MIG 7 Series - support for Artix XC7A35T and XC7A50T devices is missing in 2013.42.0 Rev2v2.0 Rev3
(Xilinx Answer 59714)MIG 7 Series - recustomization of MIG core in Vivado removes and fails to regenerate some files2.0 Rev2v2.0 Rev3
(Xilinx Answer 59515)MIG 7 Series - Vivado does not generate the correct VHDL instantiation template2.0 Rev2v2.0 Rev3
(Xilinx Answer 58636)MIG 7 Series QDRII+/RLDRAMII/3 - all multi-controller designs fail VCS and IES simulations2.0 Rev2v2.0 Rev3
(Xilinx Answer 57037)MIG 7 Series - Vivado DCP flow not supported for MIG IP2.0 Rev1v2.0 Rev22.0 Rev2
(Xilinx Answer 58195)MIG 7 Series QDRII+ - Cypress memory models give erroneous simulation results with VCS and Vivado Simulator2.0 Rev1v2.0 Rev22.0 Rev2
(Xilinx Answer 57148)MIG 7 Series QDRII+ - Latch inference on init_rd_cmd_d_reg[0]2.0 v2.0 Rev1
(Xilinx Answer 56682)MIG 7 Series QDRII+ - Write Calibration may fail for x18 multiple component designs when K/K# is not located in the same byte lane as write data2.0 v2.0 Rev1
(Xilinx Answer 55884)MIG 7 Series QDRII+ - "pi_edge_adv" can be stuck during calibration which may lead to data failures1.9.av2.0 Rev1
(Xilinx Answer 55602)MIG 7 Series QDRII+ - data failures can occur when Fixed Latency mode is enabled1.7.av2.0
(Xilinx Answer 55192)MIG 7 Series - Using ChipScope in Vivado1.9av2.0
(Xilinx Answer 54942)MIG 7 Series QDRII+ - ADDR_CTL_MAP parameter width incorrect when 4 addr/ctrl bytes used1.8.av2.0
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.5v2.0


Table 7: MIG 7 Series RLDRAMII

The following table provides known issues for MIG 7 series RLDRAMII SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 65606)MIG 7 Series QDRII+, RLDRAM2, RLDRAM3 false error message for allocation on Vref site2.4v3.0
(Xilinx Answer 67023)MIG 7 Series RLDRAM3 - Write Calibration failures can occur when Read Latency (RL) is larger than 12 2.44.1
(Xilinx Answer 65414)Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin 2.32.4
(Xilinx Answer 63640)MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen2.3N/A
(Xilinx Answer 63227)MIG 7 Series - No buffer option always expects 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz2.3v2.3 Rev1
(Xilinx Answer 62159)MIG 7 Series - Cannot generate the IP for certain configurations of RLDRAM2
2.12.3
(Xilinx Answer 60990)MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts2.0 Rev3v2.2
(Xilinx Answer 60958)MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks2.0 Rev3v2.2
(Xilinx Answer 60822)MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader"2.0 Rev32.2
(Xilinx Answer 61295)MIG 7 Series RLDRAMII - For x36 designs the QK/QK# clocks capture the wrong data byte groups2.0 Rev2N/A
(Xilinx Answer 60480)MIG 7 Series - Receiving ERROR: [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used2.0 Rev22.2
(Xilinx Answer 59517)MIG 7 Series - Running example design produces [Constraints 18-402] warnings due to invalid startpoints2.0 Rev22.1
(Xilinx Answer 58668)MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado GUI. Stand-alone support is not available even though scripts are provided.2.0 Rev22.1
(Xilinx Answer 58634)MIG 7 Series - All VHDL designs fail VCS simulations2.0 Rev1N/A
(Xilinx Answer 58621)MIG 7 Series - CRITICAL WARNING message when multiple MIG IP are added to the same project2.0 Rev1N/A
(Xilinx Answer 56387)MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains2.02.0 Rev3
(Xilinx Answer 60952)MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers2.0N/A
(Xilinx Answer 54338)MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection1.8.aN/A
(Xilinx Answer 52390)MIG 7 Series RLDRAM II / 3 - user_addr assignment incorrect in example_top module1.7.aN/A
(Xilinx Answer 61705)MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported2.1N/A
(Xilinx Answer 56228)MIG 7 Series RLDRAM II / 3 - ERROR: [Place 30-109] can occur when generating the MIG IP in batch mode1.9.aN/A
(Xilinx Answer 62322)MIG 7-series QDR/RLD memory debug signals don't show bit wise assignment on Vivado 2013.3 2014.32014.4
(Xilinx Answer 58636)MIG 7 Series QDRII+/RLDRAMII/3 - all multi-controller designs fail VCS and IES simulations2.0 Rev22.0 Rev3
(Xilinx Answer 59632)MIG 7 Series - support for Artix XC7A35T and XC7A50T devices is missing in 2013.42.0 Rev22.0 Rev3
(Xilinx Answer 59714)MIG 7 Series - recustomization of MIG core in Vivado removes and fails to regenerate some files2.0 Rev22.0 Rev3
(Xilinx Answer 59515)MIG 7 Series - Vivado does not generate the correct VHDL instantiation template2.0 Rev22.0 Rev3
(Xilinx Answer 57037)MIG 7 Series - Vivado DCP flow not supported for MIG IP2.0 Rev12.0 Rev2
(Xilinx Answer 56229)MIG 7 Series RLDRAM II / 3 - Timing failures may be seen in the MIG generated example for multi-controller designs when the Debug Port is enabled1.9.a2.0 Rev1
(Xilinx Answer 55192)MIG 7 Series - Using ChipScope in Vivado1.9.a2.0
(Xilinx Answer 55937)MIG 7 Series RLDRAM3 - initialization update to prevent data failures in hardware
1.92.0
(Xilinx Answer 55146)MIG 7 Series RLDRAM II - timing error due to high net delay in Vivado implementation1.9.a2.0
(Xilinx Answer 55138)MIG 7 Series RLDRAM II - incorrect error message for data mask pin allocation when verifying pin out in MIG GUI1.9.a2.0
(Xilinx Answer 55136)MIG 7 Series RLDRAM II - timing violation found for "u_phy_write_init_sm/rst_clk_sync_r" path
1.92.0
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.52.0


Table 8: MIG 7 Series RLDRAM3

The following table provides known issues for MIG 7 series RLDRAM3 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 67023)MIG 7 Series RLDRAM3 - Write Calibration failures can occur when Read Latency (RL) is larger than 12 2.44.1
(Xilinx Answer 65606)MIG 7 Series QDRII+, RLDRAM2, RLDRAM3 false error message for allocation on Vref site2.4v3.0
(Xilinx Answer 65414)Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin 2.32.4
(Xilinx Answer 63640)MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen2.3N/A
(Xilinx Answer 63227)MIG 7 Series - No buffer option always expects 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz2.3v2.3 Rev1
(Xilinx Answer 60992)MIG 7 Series RLDRAM3 - Simulation - Calibration failures due to issue with memory model2.0 Rev3N/A
(Xilinx Answer 60990)MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts2.0 Rev3v2.2
(Xilinx Answer 60958)MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks2.0 Rev3v2.2
(Xilinx Answer 60822)MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader"2.0 Rev32.2
(Xilinx Answer 60845)Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation2.0 Rev22.2
(Xilinx Answer 60480)MIG 7 Series - Receiving ERROR: [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used2.0 Rev22.2
(Xilinx Answer 59517)MIG 7 Series - Running example design produces [Constraints 18-402] warnings due to invalid startpoints2.0 Rev22.1
(Xilinx Answer 58668)MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado GUI. Standalone support is not available even though scripts are provided2.0 Rev22.1
(Xilinx Answer 58634)MIG 7 Series - All VHDL designs fail VCS simulations2.0 Rev1N/A
(Xilinx Answer 58621)MIG 7 Series - CRITICAL WARNING message when multiple MIG IP are added to the same project2.0 Rev1N/A
(Xilinx Answer 58562)MIG 7 Series RLDRAM3 - tWTR counter logic causes controller to lock up2.0 Rev12.0 Rev3
(Xilinx Answer 60952)MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers2.0N/A
(Xilinx Answer 56387)MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains2.02.0 Rev3
(Xilinx Answer 55419)MIG 7 Series - RLDRAM3 - extra address bits1.8.aN/A
(Xilinx Answer 54338)MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection1.8.aN/A
(Xilinx Answer 52390)MIG 7 Series RLDRAM II / 3 - user_addr assignment incorrect in example_top module1.7.aN/A
(Xilinx Answer 52231)MIG 7 Series RLDRAM 3 - Data Mask pins must be placed in the same byte lane as their corresponding data bytes1.7.aN/A
(Xilinx Answer 61705)MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported2.1N/A
(Xilinx Answer 56228)MIG 7 Series RLDRAM II / 3 - ERROR: [Place 30-109] can occur when generating the MIG IP in batch mode1.9.aN/A
(Xilinx Answer 62322)MIG 7-series QDR/RLD memory debug signals don't show bit wise assignment on Vivado 2013.32014.32014.4
(Xilinx Answer 59632)MIG 7 Series - support for Artix XC7A35T and XC7A50T devices is missing in 2013.42.0 Rev22.0 Rev3
(Xilinx Answer 59714)MIG 7 Series - recustomization of MIG core in Vivado removes and fails to regenerate some files2.0 Rev22.0 Rev3
(Xilinx Answer 59515)MIG 7 Series - Vivado does not generate the correct VHDL instantiation template2.0 Rev22.0 Rev3
(Xilinx Answer 57037)MIG 7 Series - Vivado DCP flow not supported for MIG IP2.0 Rev12.0 Rev2
(Xilinx Answer 58636)MIG 7 Series QDRII+/RLDRAMII/3 - all multi-controller designs fail VCS and IES simulations2.0 Rev22.0 Rev3
(Xilinx Answer 58635)MIG 7 Series RLDRAM3 - simulations fail when run from Vivado2.0 Rev12.0 Rev3
(Xilinx Answer 58620)MIG 7 Series RLDRAM3 - memory model out of date2.0 Rev12.0 Rev3
(Xilinx Answer 57868)MIG 7 Series RLDRAM3 - memory controller hangs when write command then read command are issued to address 01.9.a2.0 Rev1
(Xilinx Answer 56229)MIG 7 Series RLDRAM II / 3 - Timing failures may be seen in the MIG generated example for multi-controller designs when the Debug Port is enabled1.9.a2.0 Rev1
(Xilinx Answer 56217)MIG 7 Series RLDRAM 3 0 reduced bus turnaround time1.8.a2.0
(Xilinx Answer 56216)MIG 7 Series RLDRAM 3 - does not allow Data placed on T0/T3 byte groups when Data Mask and Internal Vref are enabled1.9.a2.0
(Xilinx Answer 55192)MIG 7 Series - Using ChipScope in Vivado1.9.a2.0
(Xilinx Answer 55134)MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure1.52.0


Revision History:

06/14/2014Updated for 2017.2 and added 69313
05/03/2017Removed duplicate AR 63178
04/25/2017Updated for 2017.1
02/08/2017Updated with 51456
06/09/2016updated for 2016.2
02/19/2015updated with 63640
01/23/2015updated with 62891
01/19/2015updated with 63227 and 63178
10/14/2014updated with 62322
10/14/2014updated with 62322
06/18/2014Updated for 2014.2 release
05/05/2014Added 60527
04/16/2014Updated for 2014.1 release
01/31/2014Added 59284
12/18/2013Updated for 2013.4 release
11/06/2013Added 58172
10/23/2013Added 52390, 57756, 57758, and 57760
08/28/2013Added 57221
08/16/2013Added 57148
07/11/2013Added 56682
07/02/2013Added 55013
04/18/2013Added 55165
04/15/2013Added 55531 and 55536
04/03/2013Initial release

 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
60995 MIG 7 Series - UG586 - Incorrect CKE_ODT_BYTE_MAP, CKE_MAP and ODT_MAP attributes. N/A N/A
63859 MIG - 7 Series - LPDDR2 - Simulation errors seen when simulating a MIG design N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
55129 MIG 7 Series QDRII+ - Cypress memory model fails simulation for designs with Burst Length(BL) = 2 and Data Width = 18 N/A N/A
55134 MIG 7 Series - All interfaces have pll_locked and not mmcm_locked tied to their reset structure N/A N/A
55138 MIG 7 系列 RLDRAM II — 在 MIG GUI 中验证管脚时，数据屏蔽引脚分配出现了不正确的错误消息 N/A N/A
55146 MIG 7 Series RLDRAM II - timing error due to high net delay in Vivado implementation N/A N/A
55192 MIG 7 Series - Using the ChipScope tool in Vivado Design Suite N/A N/A
55419 MIG 7 Series, RLDRAM3 - Extra address bits N/A N/A
55531 MIG 7 系列 v1.9 DDR3/DDR2 的设计咨询- 不适用于 PRBS 校正结果 (需要更新 RTL ) N/A N/A
55536 面向 MIG 7 系列 LPDDR2 的设计咨询 - 当使用“验证引脚更改和更新设计”或“固定管脚”流程时，MIG 允许执行错误的 CK/CK# 对放置 N/A N/A
55165 MIG 7 Series DDR3, Vivado Implementation - Improper high utilization of the MIG core due to signal replication from MAX_FANOUT attributes, and timing violations may also occur on signals with MAX_FANOUT attributes N/A N/A
55602 MIG 7 Series QDRII+ - Data failures can occur when Fixed Latency mode is enabled N/A N/A
55884 MIG 7 Series QDRII+ - "pi_edge_adv" can be stuck during calibration, which may lead to data failures N/A N/A
55937 MIG 7 Series RLDRAM3 - initialization update to prevent data failures in hardware N/A N/A
56216 MIG 7 Series - RLDRAM3 does not allow Data placed on T0/T3 byte groups when Data Mask and Internal Vref are enabled N/A N/A
56217 MIG 7 Series RLDRAM 3 - Reduced bus turnaround time N/A N/A
56228 MIG 7 系列 RLDRAM II / 3 - "错误：当在批处理模式下生成 MIG IP 时出现 [Place 30-109]" N/A N/A
56229 MIG 7 Series RLDRAM II / 3 - Timing failures can be seen in the MIG generated example for multi-controller designs when the Debug Port is enabled N/A N/A
56231 MIG 7 Series DDR3/2 - In some instances, the MIG default pin-out will assign an empty address/ctrl byte group N/A N/A
56276 MIG 7 Series DDR3/2 - Low bus utilization is experienced when running example design or traffic generator in hardware N/A N/A
56385 MIG 7 Series DDR3 - timing failures can occur with larger SSI devices N/A N/A
56387 MIG 7 Series - timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains N/A N/A
56451 MIG 7 Series and Virtex-6 DDR3/DDR2 - UG586 and UG406 have incorrect signal descriptions for the native interface "cmd" signal N/A N/A
56682 MIG 7 Series QDRII+ - Write Calibration might fail for x18 multiple component designs when K/K# is not located in the same byte lane as write data N/A N/A
57148 MIG 7 Series QDRII+ - Latch inference on init_rd_cmd_d_reg[0] N/A N/A
57279 MIG 7 Series DDR3 RDIMM - Clock Driver Enable settings for RC1 may cause initialization failures N/A N/A
57221 MIG 7 Series DDR3 RDIMM - Non-ideal setting for RC3/4/5 for DRAM loads of 8 or more N/A N/A
57338 MIG 7 Series DDR3 - VHDL ONLY - Designs fail during write calibration when the pin-out has a bank containing Addr/Cont groups in T0, T1, and T2 and a Data group in T3 N/A N/A
57657 MIG 7 Series - mig.prj created in XPS is not read correctly in the Vivado tool N/A N/A
57662 MIG 7 Series AXI, ECC Enabled, 4:1 - dbg_rddata_r is half the width of dbg_rddata N/A N/A
57756 MIG 7 Series DDR3 - tFAW timing parameter is set incorrectly for MT41J256m16XX-107 memory device N/A N/A
57758 MIG 7 Series DDR3/DDR2 - Vivado implementation places PLL to MMCM clock "pll_clk3" on backbone route preventing a "sys_clk" driven from a different bank from using the required route N/A N/A
57760 MIG 7 Series QDRII+ - Stage 1 calibration will always pass even if no edges are detected N/A N/A
52390 MIG 7 Series RLDRAM II / 3 - user_addr assignment incorrect in example_top module N/A N/A
57868 MIG 7 Series RLDRAM3 - memory controller hangs when write command then read command are issued to address 0 N/A N/A
58057 MIG 7 Series - IES and VCS Simulator Support N/A N/A
58172 面向 MIG 7 系列 DDR3/DDR2 的设计咨询 - MIG 包括面向 -2 / -1 速度级 2:1 (半速) DDR3/DDR2 控制器设计的错误最大频率; 数据表列出的最大规范值是正确的。 N/A N/A
57436 MIG 7 Series DDR3 - Single rank DDR3 RDIMMs incorrectly include one Chip Select (CS_n) pin when two are required; the design therefore does not program the SPD register N/A N/A
58241 2013.3 Vivado IP Integrator - MIG block diagram does not get properly updated after recustomization N/A N/A
58666 MIG 7 系列 DDR3L — MIG GUI 允许在 DDR3L (1.35V IO) 的 -1 下将比 DS182 规范 (333Mhz/667 Mbps) 高的值 (400MHz) 用于 Kintex-7 FBG N/A N/A
58667 MIG 7 Series - Out of Context (OOC) flow fails during synthesis when sys_clk is specified as "No Buffer" in the MIG 7 Series core generation N/A N/A
58668 MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado tool; standalone support is not available even though scripts are provided N/A N/A
58894 MIG 7 Series DDR3 - IP generation error message occurs for an 8Gb part N/A N/A
58647 MIG 7 Series DDR3 - Unable to derive 150 MHz input clock frequency N/A N/A
58855 MIG 7 Series DDR3/DDR2 - The AXI address width is incorrect if MIG is generated in an IPI block diagram N/A N/A
59284 MIG 7 Series DDR3/DDR2 - Manual Window Check feature does not work with VIO 2.0 N/A N/A
59606 MIG 7 Series DDR3 - Simulation fails in Vivado Simulator with ERROR: [VRFC 10-51] string is an unknown type N/A N/A
59517 MIG 7 Series - Running example design produces [Constraints 18-402] warnings due to invalid startpoints N/A N/A
59714 MIG 7 Series - recustomization of MIG core in Vivado removes and fails to regenerate some files N/A N/A
60050 MIG 7 Series DDR3/DDR2 - cmp_data_r and dbg_rddata_r are not aligned N/A N/A
60166 MIG 7 Series LPDDR2 - [Route 35-54] Net: is not completely routed N/A N/A
60687 MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1 released with Vivado 2014.2 that provide additional read margin for data rates above 1333Mbps N/A N/A
60845 Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation N/A N/A
60846 MIG 7 Series DDR3 - Kintex-7 -2L/-3L - Incorrect refclk frequency of 400MHz generated for designs operating above 1333 Mbps (667MHz) causes DRC error during implementation N/A N/A
60847 MIG 7 Series Multi-Controller - For designs with the Reference Clock set to "Use System Clock", the rtl has ref_clk connected to the last controller's input clock regardless of which controller input clock is set to 200MHz N/A N/A
60952 MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers N/A N/A
60822 MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader" N/A N/A
60958 MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks N/A N/A
60988 MIG 7 Series DDR3/DDR2 - Examples for ADDR_MAP and CK_BYTE_MAP are incorrect N/A N/A
60990 MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts N/A N/A
60992 MIG 7 Series RLDRAM3 - Simulation - Calibration failures due to issue with memory model N/A N/A
60993 MIG 7 Series DDR3 - "Memory Details" in GUI does not correctly compute density for TwinDie custom parts N/A N/A
61295 MIG 7 Series RLDRAMII - For x36 designs the QK/QK# clocks capture the wrong data byte groups N/A N/A
61356 MIG 7 系列 - Artix-7 CSG235 只包含 HR bank，但 MIG Bank 选择页面显示 Bank 34 为 HP。 N/A N/A
61576 MIG 7 Series DDR3 - After re-customizing, ECC will become "Disabled" even though it was originally "Enabled" N/A N/A
61705 MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported N/A N/A
61790 7 Series MIG - DDR3 - app_rd_data_end stays high N/A N/A
61805 MIG 7 Series - LPDDR2 calibration fails in Phase Detection when memory operating frequency is 200MHZ N/A N/A
62159 MIG 7 系列——不能生成 IP 用于 RLDRAM-II 的特定配置 N/A N/A
62161 MIG 7 series - Errors that don't mean anything to the user are flagged when trying to customize the MIG core. N/A N/A
62160 MIG 7 series - Is Dynamic ODT supported? N/A N/A
62320 MIG 7 Series DDR2 - DQS overshoot on 200MHz design when CL=3 N/A N/A
62322 MIG 7-series QDR/RLD memory debug signals don't show bit wise assignment on Vivado 2013.3 N/A N/A
58307 MIG 7series - IPI block design Interrupt signal direction is incorrect N/A N/A
63227 MIG 7 Series - No buffer option always expects 200Mhz on clk_ref_i and instantiates additional MMCM for 300 or 400Mhz N/A N/A
63178 MIG 7 系列 - DDR3 – 采用 2:1 控制器进行仿真时，地址/命令总线上出现小故障 N/A N/A
63122 MIG 7 Series DDR2/DDR3 v2.3 - Automated and manual write window margin check feature is not available on the example design N/A N/A
63165 MIG 7 Series DDR2/DDR3 v2.3- Additional BUFG added in "opt_design" for the "freq_refclk" can lead to minimum pulse width timing violations N/A N/A
63640 MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen N/A N/A
64237 MIG 7 Series - Timing parameter values are incorrect for certain memory parts N/A N/A
65355 MIG 7 series - IP OOC synthesis run goes out-of-date when "Validate Design" is run on the block design N/A N/A
65414 Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin N/A N/A
65606 MIG 7 Series QDRII+, RLDRAM2, RLDRAM3 false error message for allocation on Vref site N/A N/A
66181 MIG 7 Series DDR3 - IBUF_LOW_PWR may be incorrectly enabled in Vivado 2015.1 and 2015.2 N/A N/A
64421 MIG 7 Series - DDR3 AXI design with ECC fails in Hardware N/A N/A
66140 MIG 7 series (LPDDR2) - Incorrect width of app_wdf_mask signal seen in instantiation template and top level file N/A N/A
66422 MIG 7 Series - Debug Signals are not available when using IP Integrator N/A N/A
66788 Design Advisory for MIG 7 Series DDR3 - DQS_BIAS is not properly enabled for HR banks causing potential calibration failures N/A N/A
66892 MIG 7 Series - DDR3 Custom part simulation may fail with Undefined variable: TDQSCK_DLLDIS N/A N/A
66969 MIG 7 Series - Cannot select 72-bit data width in the MIG wizard GUI when the part is XC7Z035FFG676-2 N/A N/A
67179 MIG 7 Series - Memory clock period range is updated in Vivado 2016.2 and may cause errors during IP upgrade N/A N/A
69222 Zynq UltraScale+ MPSoC - What PHY devices are tested with the Zynq MPSoC CAN controller? N/A N/A
69313 MIG 7 Series - Notification when Modifying Default MIG Parameters for Artix-7 or Spartan-7 Devices with DDR3, DDR3L, or LPDDR2 Interfaces N/A N/A
AR# 54025
日期 10/16/2017
状态 Active
Type 版本说明
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
Tools
  • Vivado Design Suite
IP
  • MIG 7 Series

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