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| MIG 7 Series - Tactical Patch - 2018.3 Known Issues | 4.2 | 未解决 |
| MIG 7 Series - Notification when Modifying Default MIG Parameters for Artix-7 or Spartan-7 Devices with DDR3, DDR3L, or LPDDR2 Interfaces | 4.0 rev3 | N/A |
| MIG 7 Series - Critical Warning during Synthesis of MIG Design with XC7S6 or XC7S15 Spartan-7 Devices | 4.2 | 未解决 |
| MIG 7 Series - Memory clock period range is updated in Vivado 2016.2 and may cause errors during IP upgrade | N/A | N/A |
| MIG 7 Series DDR3 - Periodic reads used for VT tracking may be missing during continuous write transactions | 1.9 | 4.0 rev1 |
| MIG 7 Series - IP GUI crashes when clicking "browse" button on Windows 8 or Windows 10 | 3.0 | 4.0 rev1 |
| MIG 7 Series - Can not select 72-bit data width in the MIG wizard GUI when the part is XC7Z035FFG676-2 | 2.4 rev1 | 4.0 rev1 |
| MIG 7 Series - Critical warnings occur when multiple MIG IP are added to the same project | 2.0 Rev1 | 未解决 |
| MIG 7 Series DDR3/DDR2 - cmp_data_r and dbg_rddata_r are not aligned | 2.0 | 未解决 |
| MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers | 2.0 | 未解决 |
| MIG 7 Series - FATAL error seen during simulation of MIG example design | 2.3 Rev2 | N/A |
| MIG 7 Series - IP OOC synthesis run goes out-of-date when "Validate Design" is run on the block design | 2.3 Rev2 | N/A |
| MIG 7 Series DDR2/DDR3 v2.3 - Automated and manual write window margin check feature is not available on example design | 2.3 | N/A |
| MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen | 2.3 | N/A |
| MIG 7 Series - Errors when regenerating a remotely sourced MIG core in customers larger design | 2.3 | N/A |
| MIG 7 Series - Crashes when Read XDC/UCF option is used in Windows 8.1 | 2.3 | N/A |
| MIG 7 系列 - DDR3 – 采用 2:1 控制器进行仿真时，地址/命令总线上出现小故障 | 2.3 | N/A |
| MIG 7 Series - No buffer option always expects 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz | 2.3 | N/A |
| MIG 7 Series - Multi-controller designs require custom part to be created for each controller | 2.3 | N/A |
| 面向 MIG 7 系列 DDR3 的设计咨询——Vivado 2014.4 版配套提供的 MIG 7 系列 v2.3 版校准更新提供了更多的写入裕度。 | 2.3 | N/A |
| MIG 7 Series DDR3 - Calibration updates to improve read and write margin result in an increase in calibration time starting with MIG v2.1 released with Vivado 2014.2.Is there a way to reduce the calibration time? | 2.2 | N/A |
| MIG 7 Series DDR3 (IPI flow ONLY) - Warning message generated upon IPI Upgrade - Clocking structure for MIG has been updated | 2.2 | N/A |
| MIG 7 Series AXI DDR3/DDR2 Enabling Narrow Burst option within MIG does not affect the RTL and the parameter remains set to '0' | 2.2 | N/A |
| MIG 7 Series - Errors that do not mean anything to the user are flagged when trying to customize the MIG core | 2.1 | N/A |
| MIG 7 Series - DDR3 - app_rd_data_end stays high | 2.1 | N/A |
| MIG 7 Series - the funcsim.v/.vhdl structural simulation model is not supported | 2.1 | N/A |
| 面向 MIG 7 系列 DDR3 的设计咨询 - DIMM 接口的数据速率规范更改和组件接口的数据速率咨询 | 2.1 | N/A |
| MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1 released with Vivado 2014.2 that provide additional read margin for data rates above 1333Mbps | 2.1 | N/A |
| MIG 7 Series DDR3 - Traffic Generator detects false error messages when VIOs are used to change the data modes | 2.0 | N/A |
| MIG 7 Series - DDR3, LPDDR2, and DDR2 support changes for Virtex-7 HT devices | 1.9a | N/A |
| MIG 7 Series - Needed XDC constraint changes when using a Synplify netlist within Vivado | 1.8a | N/A |
| MIG 7 Series DDR3/2 - In some instances, the MIG default pin-out will assign an empty address/ctrl byte group | 1.6 | N/A |
| MIG 7 Series DDR3 - 48-bit design unable to fit into 2 HP banks | 1.6 | N/A |
| MIG 7 Series - DDR3 Custom part simulation may fail with undefined variable:TDQSCK_DLLDIS | 2.4 | 3.0 |
| Design Advisories for MIG 7 Series -DDR3 DQS_BIAS is not properly enabled for HR banks causing potential calibration failures. | 2.3 | 3.0 |
| MIG 7 series - GUI shows incorrect tested Vivado version number | 2.3 Rev2 | v2.4 |
| MIG 7 Series DDR3 - IBUF_LOW_PWR may be incorrectly enabled in Vivado 2015.1 and 2015.2 | 2.3 Rev1 | v2.4 |
| MIG 7 Series DDR2/DDR3 v2.3 - Maximum speed for dual rank/twin die DDR3 is updated | 2.3 | 2.3 Rev1 |
| MIG 7 Series DDR2/DDR3 v2.2/2.3- Additional BUFG being added in "opt_design" on the "freq_refclk" can lead to minimum pulse width timing violations | 2.3 | 2.3 Rev1 |
| MIG 7 Series - Virtex-7 HT - Error is generated when trying to open MIG 7 Series tool when targeting a part with an flg package - Failed to generate custom UI outputs | 2.0 Rev3 | 2.3 Rev1 |
| MIG 7 Series DDR3/DDR2 - Manual Window Check feature does not work with VIO 2.0 | 2.0 | 2.3 Rev1 |
| MIG 7 Series - DDR3 - 72-bit AXI4 interface generated with ECC disabled | 2.2 | v2.3 |
| MIG 7 series - GUI restricts to select required Clock Period that was allowed in earlier MIG versions | 2.2 | v2.3 |
| MIG 7 series - IPI Design Create Clock Constraint Critical Warning -Constraints 18-1056 Clock 'sys_clk' completely overrides clock 'sys_diff_clock_clk_p' | 2.1 | v2.3 |
| MIG 7 series - Is Dynamic ODT supported? | 2.1 | v2.3 |
| MIG 7 Series - UG586 - Incorrect CKE_ODT_BYTE_MAP, CKE_MAP and ODT_MAP attributes | 2.0 Rev3 | v2.3 |
| MIG 7 Series DDR3 - "Memory Details" in GUI does not correctly compute density for TwinDie custom parts | 2.0 Rev3 | v2.3 |
| MIG 7 Series - User Guide button in the GUI results in an ERROR popup - "PDF Viewer not Found: Could not open Acrobat Reader" | 2.0 Rev3 | v2.3 |
| MIG 7 Series Multi-Controller - For designs with the Reference Clock set to "Use System Clock", the rtl has ref_clk connected to the last controller's input clock regardless of which controller input clock is set to 200MHz | 2.1 | v2.3 |
| MIG 7 Series DDR3 - Kintex-7 -2L/-3L - Incorrect refclk frequency of 400MHz generated for designs operating above 1333 Mbps (667MHz) causes DRC error during implementation | 2.1 | v2.3 |
| MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2.Errors were not seen in previous versions. | 2.1 | v2.2 |
| MIG 7 Series - cannot generate data width greater than 8-bits for CPG325 packages | 2.1 | v2.2 |
| MIG 7 Series DDR3 - After re-customization, ECC will become "Disabled" even though it was originally "Enabled" | 2.1 | v2.2 |
| MIG 7 系列 - Artix-7 CSG235 只包含 HR bank，但 MIG Bank 选择页面显示 Bank 34 为 HP。 | 2.1 | v2.2 |
| MIG 7 Series - Pin Compatible feature does not work on Artix automotive parts | 2.0 Rev3 | v2.2 |
| MIG 7 Series DDR3/DDR2 - Examples for ADDR_MAP and CK_BYTE_MAP are incorrect | 2.0 Rev3 | v2.2 |
| MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks | 2.0 Rev3 | v2.2 |
| MIG 7 Series - Receiving ERROR: [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used | 2.0 Rev2 | v2.2 |
| MIG 7 Series DDR3 - VCS simulations fail with unresolved modules | 2.0 Rev3 | v2.2 |
| MIG 7 Series - Out of Context (OOC) flow fails during synthesis when sys_clk is specified as "No Buffer" in the MIG 7 Series core generation. | v1.9 | v2.2 |
| MIG 7 Series - Artix-7 - MIG 7 Series will not open for xq7a200t devices | 2.0 Rev3 | v2.1 |
| MIG 7 Series - Running example design produces [Constraints 18-402] warnings due to invalid start points | 2.0 Rev2 | v2.1 |
| MIG 7 Series - All VHDL designs fail VCS simulations | 2.0 Rev1 | v2.1 |
| MIG 7 Series DDR3 - issues with sys_clk type in ZC706 reference design | 2.0 Rev1 | v2.1 |
| MIG 7 Series - support for Artix XC7A35T and XC7A50T devices is missing in 2013.4 | 2.0 Rev2 | 2.0 Rev3 |
| MIG 7 Series - customization of MIG core in Vivado removes and fails to regenerate some files | 2.0 Rev2 | 2.0 Rev3 |
| MIG 7 Series - Vivado does not generate the correct VHDL instantiation template | 2.0 Rev2 | 2.0 Rev3 |
| MIG 7 Series DDR3 - Simulation fails in Vivado Simulator with ERROR: [VRFC 10-51] string is an unknown type | 2.0 Rev2 | 2.0 Rev3 |
| MIG 7 Series DDR3 - Unable to derive 150MHz input clock frequency | 2.0 Rev2 | 2.0 Rev3 |
| MIG 7 Series DDR3 - IP generation error message occurs for 8Gb part | 2.0 Rev2 | 2.0 Rev 3 |
| MIG 7 Series - Simulation of the MIG example designs using XSIM must be run through the Vivado GUI.Stand-alone support is not available even though scripts are provided. | 2.0 Rev2 | 2.0 Rev 3 |
| MIG 7 Series DDR3/DDR2 - MIG GUI allows higher value (400MHz) than the DS191 specification (333Mhz/667 Mbps) for Kintex-7 FBG in -1 for DDR3L (1.35V IO) | 2.0 Rev 1 | 2.0 Rev 3 |
| MIG 7 Series DDR3 RDIMM - non-ideal setting for RC3/4/5 for DRAM loads of 8 or more | 2.0 | 2.0 Rev 3 |
| MIG 7 Series - Timing failures within the VIO/ILA 2.0 can occur across all interfaces when using multiple clock domains | 2.0 | 2.0 Rev 3 |
| MIG 7 Series - Vivado DCP flow not supported for MIG IP | 2.0 Rev1 | 2.0 Rev2 |
| MIG 7 Series DDR3/DDR2 - MIG includes incorrect maximum frequencies for 2:1 (half-rate) DDR3/DDR2 controller designs targeting -2 and -1 speed grades.数据表列出的最大规范值是正确的。 | 2.0 Rev1 | 2.0 Rev2 |
| MIG 7 Series DDR3/DDR2 - The AXI address width is incorrect if MIG is generated in an IPI block diagram | 2.0 | 2.0 Rev2 |
| MIG 7 Series - mig.prj created in XPS is not read correctly in Vivado | 2.0 | 2.0 Rev1 |
| MIG 7 Series DDR3 - Timing failures can occur with larger SSI devices | 2.0 | 2.0 Rev1 |
| MIG 7 Series AXI - ECC Enabled - 4:1 - dbg_rddata_r is half the width of dbg_rddata | 2.0 | 2.0 Rev1 |
| MIG 7 Series DDR3 RDIMM - Clock Driver Enable settings for RC1 may cause initialization failures | 2.0 | 2.0 Rev1 |
| MIG 7 Series DDR3 - VHDL ONLY - Designs fail during write calibration when the pin-out has a bank containing Addr/Cont groups in T0, T1, and T2 and a Data group in T3 | 1.9 | 2.0 Rev1 |
| MIG 7 Series DDR3 - dbg_dqs VIO selection is not connected to mux_rd_rise/fall signals in debug cores | 1.8a | 2.0 Rev1 |
| MIG 7 系列- DDR3 –控制器在 read-modify-write 操作中挂起。 | 1.8.a | 2.0 Rev1 |
| MIG 7 Series DDR3/DDR2 - Vivado implementation places PLL to MMCM clock "pll_clk3" on backbone route preventing a "sys_clk" driven from a different bank from using the required route | 1.7a | 2.0 Rev1 |
| MIG 7 Series DDR3 - ChipScope Debug Signal connections for OCLKDELAY calibration are out of date after installing patch from Answer Record 53420 | 1.7a | 2.0 Rev1 |
| MIG 7 Series DDR3 - Single rank DDR3 RDIMMs incorrectly include one Chip Select (CS_n) pin when two are required.The design therefore does not program the SPD register. | 1.7 | 2.0 Rev1 |
| Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied | 1.9.a | 2.0 |
| MIG 7 Series DDR3, Vivado Implementation - Improper high utilization of the MIG core is seen due to signal replication from MAX_FANOUT attributes.Timing violations may also be seen on signals with MAX_FANOUT attributes | 1.9.a | 2.0 |
| MIG 7 Series - Using ChipScope in Vivado | 1.9.a | 2.0 |
| MIG 7series - IPI block design Interrupt signal direction is incorrect | 1.9 | 2.0 |
| MIG 7 Series DDR3 - The MIG 7 Series tool does not allow selecting 800 MHz for dual rank DIMMs in a -2 FPGA design when a 1.35V/1,5V part is selected using the 1.5V option | 1.8.a | 2.0 |
| MIG 7 Series DDR3 - PRBS Read Leveling Debug signals are not connected to dbg_dqs VIO control | 1.8a | 2.0 |
| MIG 7 Series DDR3/DDR2 - MAX_FANOUT attribute not being honored | 1.8.a | 2.0 |
| MIG 7 Series DDR3/DDR2 - Timing violations may be seen in 2:1 designs running around 533 MHz within u_ddr_mc_phy | 1.8.a | 2.0 |
| MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected | 1.8.a | 2.0 |
| MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts | 1.8.a | 2.0 |
| MIG 7 Series DDR3/DDR2 - AXI Interface Enabled - Controller services write command before read is completed. | 1.8.a | 2.0 |
| MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure | 1.5 | 2.0 |