I have exported an EDIF file from a Vivado project in order to use it as a submodule of another project.
Then, I added the .edf file to my new project and instantiated it in a top level. The design hierarchy looks correct, but synthesis says the submodule is not found.
If I export Verilog for the submodule and instantiate it in the same top level, it works fine.
Is there any limitation when using edif output generated from write_edif?
Functionally, both the exported EDIF and the Verilog structural netlist should work in the post synthesis design.
However, during synthesis (only) an RTL based synthesis "stub" is required for lower level modules that are available as EDIF (or NGC) only.
If your top level is VHDL, a component declaration is the most common way to specify this.
However, if your top level is Verilog, you will need to supply a Verilog empty module corresponding to the lower level EDIF module (with matching ports) to satisfy the synthesis stub requirement.
When your lower level is structural Verilog, that module definition directly works, so no extra stub file is necessary.
For EDIF export, you can additionally export a synthesis stub file from the same design, with just the ports, as shown below:
2017.4 and prior:
write_verilog -mode port module_stub.v
write_verilog -mode synth_stub module_stub.v
Now, if you add both module.edf and module_stub.v to the project, things will work.
The stub file will be used during synthesis only, the module will remain a black box during synthesis, but the EDIF will automatically be used to resolve the black box in your post synthesis design.