Production devices incorporate low power features that resulted new checks in the Boot ROM to sense voltage issues at boot. As a result, marginal designs might boot in Engineering Sample (ES) parts but fail with Production parts.
Depending on power supply integrity on the VCCPLL domain, the boot operation might not complete under the following conditions:
This issue can also occur in the low voltage mode if the PS PLLs have been disabled and two or more of the three PS PLLs are enabled simultaneously at any point in time. This can occur because when the PS PLLs are enabled and start to lock, more current draw (mA range) on VCCPLL occurs. The current draw frequency is at the PLL reference clock frequency (between 30 and 60 MHz).
VCCPLL is a 1.8V nominal supply that provides power to the three PS PLLs and additional analog circuits. It can be powered separately or derived from the VCCPAUX supply. If powered by VCCPAUX, VCCPLL must be filtered through a 120 Ohm @ 100 MHz, size 0603 ferrite bead and a 10 uF or larger, size 0603 decoupling capacitor. In both cases a 0.47 uF to 4.7 uF 0402 capacitor must be placed near the VCCPLL BGA via.
The PCB construction of the VCCPLL power supply must be carefully managed. The recommended connection between the 10 F 0603 capacitor and the VCCPLL BGA ball is a planelet with a minimum width of 80 mil (2 mm) and a length of less than 3,000 mil (76 mm). If a planelet cannot be used, then a trace with a maximum impedance of 40 Ohm and a length of less than 2,000 mil (50.8mm) must be used. The 0.47 uF to 4.7 uF 0402 or 0201 capacitor must have a less than a 200 mil (5.1 mm) total PCB trace length from the capacitor to the adjacent VCCPLL and GND BGA vias.
For full details, please consult UG933 v1.3 or later.