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AR# 54230

Design Advisory for 14.x Timing Analysis for Spartan3a/Spartan3an/Spartan3e/Virtex4/Virtex5/6 Series/7 Series - Timing Score increases due to hold violations

Description

This Design Advisory was most recently updated on February 14th, 2013, with the following details below:

The ISE Design Suite 13.3 and older versions of TRCE/Timing Analyzer tools had incorrect hold analysis requirements for cross-clock domain paths with out-of-phase clocks for Spartan3a/Spartan3an/Spartan3e/Virtex4/Virtex5/6 series/7 series designs. This has been addressed in ISE Design Suite 13.4 and newer versions, which caused the requirement for hold analysis to get smaller or more restrictive for cross-clock domain paths.The hold requirement for cross-clock domain paths is to include the phase difference between the launching clock and the capturing clock. This smaller requirement has caused the timing score to increase.

解决方案

The following are the steps needed to review the impact of this change on your design in ISE Design Suite 13.4 and newer versions:

  1. Check the clock topology of your design
  2. Assess timing analysis results for an increase in the timing score. If necessary, update the failing designs


Details:

1. Check the clock topology of your design

A. Review the clocking structure for cross-clock-domain paths. If you have constrained data paths between clock domains, continue to step B.
B. Review the phase relationship between the clock domains. If your clocks are not even multiples of each other, continue to the step 2.

2. Assess timing analysis results for an increase in the timing score
A. Run the design through timing analysis using ISE Design Suite 13.4 or newer version. Example: 'trce -e 4 design.ncd design.pcf' or 'timingan'
B. If the design passes timing analysis with no errors, no further action is necessary. Design in the field are not affected by this change if timing analysis has passed. Designs in progress should continue to use the latest ISE Design Suite 14.x for further development.
C. If the design fails timing analysis, the design must be updated so that it passes timing analysis and a new bitstream must be generated.
    3. Update the failing design
    A. ISE and PlanAhead Software Users
        • Option 1: Re-run the Place-and-Route process. If timing analysis passes with the newly routed design, continue to bitstream creation.
        • Option 2: Re-run the MAP and Place-and-Route process. If timing analysis passes with the newly routed design, continue to bitstream creation.
    B. Command Line Users
        • Option 1: Re-run PAR with Re-Entrant Routing (par -k). If timing analysis passes with the newly routed design, continue to bitstream creation.
        • Option 2. Re-run PAR on full design. If timing analysis passes with the newly routed design, continue to bitstream creation.

    链接问答记录

    主要问答记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    40835 Design Advisory for Xilinx Timing Solution Center N/A N/A
    AR# 54230
    创建日期 02/12/2013
    Last Updated 02/25/2013
    状态 Active
    Type 设计咨询
    器件
    • Artix-7
    • Kintex-7
    • Virtex-4
    • More
    • Virtex-5
    • Virtex-7
    • Virtex-6
    • Spartan-6
    • Spartan-3A
    • Spartan-3A DSP
    • Spartan-3AN
    • Spartan-3E
    • Less
    Tools
    • ISE Design Suite - 13.4
    • ISE Design Suite - 14.3
    • ISE Design Suite - 14.4
    • More
    • ISE Design Suite - 14.2
    • ISE Design Suite - 14.1
    • Less