描述

This answer record contains the Release Notes and Known Issues for the Aurora 64B66B Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History
  

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please see XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Aurora 64B/66B LogiCORE IP Page:

https://www.xilinx.com/products/intellectual-property/aurora64b66b.html

解决方案

General Information

Supported devices can be found in the following three locations:

• Aurora 64B66B LogiCORE Product Guide
• Aurora 64B66B LogiCORE IP Page - https://www.xilinx.com/content/xilinx/en/products/intellectual-property/aurora64b66b.html
• Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

• General: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
• General: Updated the initial value being driven in example design simulation top for PMA_INIT input
• Revision change in one or more subcores

Changes in v11.2 Rev3:

• Bug Fix: Fixed CDC warning for HLD_POLARITY_OUT signal.
• Revision change in one or more subcores

Changes in v11.2 Rev2:

• General: FIFO Generator version upgrade.
• General: updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
• Revision change in one or more subcores

Changes in v11.2 Rev1:

• Bug Fix: for multi-quad GTY based designs with line rate of more than 16.375 Gbps the reference clock locations are added in XDC
• Other: UltraScale GT Wizard version upgrade. 

Changes in v11.2:

• New Feature: UltraScale GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
  
• Revision change in one or more subcores 

Changes in v11.1 Rev3:

• Revision change in one or more subcores
  

Changes in v11.1 Rev2:

• Feature Enhancement: Added Advanced RX GT Options selection in GUI for UltraScale devices
• Feature Enhancement: Added support for GTYE4 up to 25.7813 Gbps line rates
• Feature Enhancement: Updated support for GTYE3 up to 25.7813 Gbps line rates
• Revision change in one or more subcores
  

Changes in v11.1 Rev1:

• COMMON_CFG[6] attribute value updated for configurations with QPLL on GTHE2 Transceiver based devices
• Revision change in one or more subcores

Changes in v11.1:

• Improved Performance and Utilization for GTY designs in Framing mode
• Added feature to preview shared logic files when Shared logic in Example Design option is selected
• Removed the dependency on gtwiz_reset_rx_cdr_stable_out from GT channel to re-initialize the core for UltraScale Devices
• Added gt_rxusrclk_out optional port when Additional transceiver control and status ports option is enabled
• Revision change in one or more subcores

Changes in v11.0 Rev1:

• Added support for new speed grades of XQ7K325T and XQ7K410T devices
• Added support for new speed grades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
• Revision change in one or more subcores
  

Changes in v11.0:

• Added core support for GTY transceiver
• Core architecture modified for GTY timing optimization
• Added line rate support up to 25G
• GTREFCLK input clocking architecture modified for GTY with line rate above 16.375G
• CRC architecture for line rates above 16.375G modified
• UFC and USERK interfaces not supported for line rate above 16.375G
• Added support for XC7Z030SBV485 and XC7Z030ISBV485 devices
• UltraScale GT Wizard and FIFO subcore versions updated
• s_axi_user_k_tx_tready output gated with channel_up
• TXMASTERCHANNEL and RXMASTERCHANNEL selection updated for UltraScale transceivers

Changes in v10.0 (Rev1):

Added support for XQ7Z045RFG676, XQ7Z100RF1156 and XQ7VX690TRF1158 devices

Changes in v10.0:

• Added support for 7 Series devices with FFV and FBV Pb-Free packages
• Max line rate support of 16.375G added for UltraScale GTH devices
• Added support for Simplex Auto recovery
• Added txinhibit and pcsrsvdin optional transceiver control and status ports
• Both pma_init and reset_pb ports made asynchronous to the core; reset, tx_reset and rx_reset input ports removed
• Standard CC module made part of the IP, do_cc port removed
• Flow control AXI ports grouped into AXI4 Stream interfaces
• Control and status ports are grouped as display interfaces
• Added support for single ended clocking option to INIT_CLK and GTREFCLK
• Added support for contiguous lane selection for UltraScale devices
• CRC resource utilization optimized
• GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
• Line rate value restricted to 4 decimal digits for UltraScale devices
• INIT clock frequency value restricted to 6 decimal digits

Changes in v9.3Rev2:

• UltraScale GT Wizard version updated

Changes in v9.3 Rev1:

• Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI, XC7K480TI, XC7Z030I, XC7Z035, XC7Z035I, XC7Z045I, XC7Z100I devices
• Minor update to XDC for board support

Changes in v9.3:

• Added support for XA7Z030 devices.
• UltraScale GT Wizard version updated.
• Core resets separated for TX/RX_Simplex dataflow configuration.
• AXI4-LITE protocol compliant GT DRP interface with optional ports added.
• Per lane AXI4-LITE GT DRP interface supported for 7 Series core.
• Added support for user configurable DRP clock and INIT clock through IP GUI.
• User selectable option enabled for GT DRP interface in IP-Integrator.
• Added support for auto-propagate to INIT and DRP clock in IPI systems.
• Addressed CPLL power down circuit requirement for 7 Series Transceivers - refer to AR.
• Added support for Xilinx Evaluation platform boards.
• XDCs compliant with updated timing constraining guidelines.
• Differential INIT clock input added to UltraScale example design.
• Included GT reset staging in example design, when lab tools option in GUI is disabled.
• mmcm_not_locked_out polarity changed to active high for UltraScale.
• PMA_RSV attribute setting updated for 7 Series GTH designs.

Change in v9.2 (Rev. 1):

• UltraScale GT Wizard version upgrade.
• Fixed Simplex designs which were returning the error "Failed to open info file xil_defaultlib/_info" in read mode.
• PMA_RSV attribute setting updated for 7 Series GTH designs.
• Fixed hold violation timing issues in UltraScale device based designs.
• Added missing synchronizers in clocking core for UltraScale designs.
• GT_DIRECTION set as BOTH,TX_ENABLE & RX_ENABLE set as TRUE for UltraScale designs.

• Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
• Added support for UltraScale devices
• Enhanced support for IP Integrator
• Added Little endian support for PDU, UFC and NFC interfaces as non-default GUI selectable option
• Interoperability guidance provided in Product Guide
• Resolved functional issue seen with specific frame length in certain scenarios

Change in v9.1:

• Increased the number of optional transceiver control and status ports
  

Changes in v9.0:

• Provided Verilog source and VHDL netlist
• TX startup state machine update for MMCM lock synchronization with stable clock
• RX startup state machine updates to handle the RX Reset after valid data is received
• Linear 32-bit data path interface from GT RX
• Lane skew tolerance enhancement, now able to tolerate more lane to lane skew
• Polarity inversion logic is enabled
• Common reset and controls across all lanes
• Increased the Rx CDR lock time from 50KUI to 37MUI as suggested by GT user guide
• Increased the Block sync header max count from 64 to 60K to increase the robustness of the link
• Transmission of more idle characters to add more robustness to link
• Channel_INIT state machine and TX startup state machine are updated for hot plug sequence
• Removed the reset to scrambler and made it free running to achieve faster CDR lock
• Fixed corner case packet drop during CC (Clock Correction) insertion
• Updated GTH QPLL attributes - Refer to (Xilinx Answer 56332)
• Ease Of Use Updates. For details, refer to migrating and upgrading section of Product Guide
• Added GUI option to include or exclude shareable logic resources in the core
• Added optional transceiver control and status ports
• Updated synchronizers for clock domain crossing to reduce "Mean Time Between Failures" (MTBF) from meta-stability
• Reduced warnings in synthesis and simulation
• Added support for Cadence IES and Synopsys VCS simulators
• Basic Support for IP Integrator
• XDC constraints updated to constrain 1st stage of the synchronizer flop
• Added GUI option to include or exclude Vivado Lab tools support for debug
• Added quality counters in example design to increase the test quality
• Added hardware reset state machine in example design to perform repeat reset testing

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE Aurora 64B66B core.

Known and Resolved Issues

The following table provides known issues for the Aurora 64B66B core, starting with v8.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Notes:

1. AXI4_LITE based DRP interface is not fully AXI4_LITE compliant. This is fixed with v9.3 release
2. XDC files of Vivado and CORE Generator tool versions differ in 14.4/2012.4. This is fixed in v8.0

Revision History: