This answer record contains the Release Notes and Known Issues for the AXI GPIO and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.4 and older tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
AXI GPIO LogiCORE IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
The table below provides answer records for general guidance when using the LogiCORE IP AXI GPIO.
|(Xilinx Answer 55248)||Vivado Timing and IP Constraints|
|(Xilinx Answer 51779)||Zynq-7000 SoC Example DesignsZynq-7000 AP SoC Example Designs|
|(Xilinx Answer 39412)||12.3 EDK, AXI_GPIO - ip2bus_wrack and ip2bus_rdack are 'X' during simulation|
Known and Resolved Issues
The following table provides known issues for the AXI GPIO, starting with v2.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
04/03/2013 - Initial release
12/18/2013 - Updated for 2013.4