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  3. AR# 54487: IP Release Notes and Known Issues for LogiCORE 3GPP LTE RACH Detector core for Vivado 2013.1 and Forward

AR# 54487

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IP Release Notes and Known Issues for LogiCORE 3GPP LTE RACH Detector core for Vivado 2013.1 and Forward

描述

This answer record contains the Release Notes and Known Issues for the LogiCORE 3GPP LTE RACH Detector core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE 3GPP LTE RACH Detector core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-rach-lte.html

解决方案

General Information

Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Core Version Vivado Tools Version
v2.0(Rev. 4) 2014.1
v2.0(Rev. 3) 2013.4
v2.0(Rev. 2) 2013.3
v2.0(Rev. 1) 2013.2
v2.0 2013.1

General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE 3GPP LTE RACH Detector core.
Article Number Article Title
N/A N/A


Known and Resolved Issues
The following table provides known issues for the LogiCORE 3GPP LTE RACH Detector core, starting with v2.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
 
Article Number Article Title Version Found Version Resolved
(Xilinx Answer 59797) Behavioral simulation using Synopsys VCS simulator may give incorrect outputs v2.0(Rev. 4) N/A
(Xilinx Answer 56292) The C-model differs from the core in the least significant bits of the output v2.0 N/A
(Xilinx Answer 56245) Simulation failure occurs in the Vivado(2013.1) post-synthesis Verilog model v2.0 N/A
(Xilinx Answer 53465) Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>? v1.0 v2.0
(Xilinx Answer 45669) What is the data width for the carrier frequency FC? v1.0 N/A
(Xilinx Answer 45663) What is the range for the physical root sequence? v1.0 N/A
(Xilinx Answer 45662) Is the root sequence described in the data sheet the physical root sequence index or logical root sequence index? v1.0 N/A
(Xilinx Answer 38686) What is the correct description for the Fc offset demodulation value described in data sheet DS761? v1.0 N/A


Revision History:
03/17/2014 - Added (Xilinx Answer 59797)
04/03/2013 - Initial Release

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
45662 LogiCORE LTE RACH Detector v1.0 - Is the root sequence described in the data sheet the physical root sequence index or logical root sequence index? N/A N/A
38686 LogiCORE LTE RACH Detector v1.0 - What is the correct description for the Fc offset demodulation value described in data sheet DS761? N/A N/A
45663 LogiCORE LTE RACH Detector v1.0 - What is the range for the physical root sequence? N/A N/A
45669 LogijCORE LTE RACH Detector v1.0 - What is the data width for the carrier frequency FC? N/A N/A
56245 LogiCORE IP LTE RACH Detector v2.0 - Simulation failure occurs in the Vivado 2013.1 post-synthesis Verilog model N/A N/A
59797 LogiCORE IP LTE Rach Detector v2.0(Rev. 4) - Behavioral simulation using Synopsys VCS simulator may give incorrect results N/A N/A
AR# 54487
日期 11/10/2014
状态 Active
Type 版本说明
IP
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