(Xilinx Answer 59797) |
Behavioral simulation using Synopsys VCS simulator may give incorrect outputs |
v2.0(Rev. 4) |
N/A |
(Xilinx Answer 56292) |
The C-model differs from the core in the least significant bits of the output |
v2.0 |
N/A |
(Xilinx Answer 56245) |
Simulation failure occurs in the Vivado(2013.1) post-synthesis Verilog model |
v2.0 |
N/A |
(Xilinx Answer 53465) |
Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>? |
v1.0 |
v2.0 |
(Xilinx Answer 45669) |
What is the data width for the carrier frequency FC? |
v1.0 |
N/A |
(Xilinx Answer 45663) |
What is the range for the physical root sequence? |
v1.0 |
N/A |
(Xilinx Answer 45662) |
Is the root sequence described in the data sheet the physical root sequence index or logical root sequence index? |
v1.0 |
N/A |
(Xilinx Answer 38686) |
What is the correct description for the Fc offset demodulation value described in data sheet DS761? |
v1.0 |
N/A |