This answer record contains the Release Notes and Known Issues for the Zynq UltraScale+ VCU DDR Controller and includes the following:
Zynq UltraScale+ VCU DDR Controller Page:
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Supported Devices can be found in the following three locations:
Note: the Zynq UltraScale+ VCU DDR Controller is only supported for Zynq UltraScale+ VCU Applications (H.264/H.265 Video Codec Unit) in the Zynq UltraScale+ EV parts.
For a list of new features and added device support for all versions:
Table 1: Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version||IP Changelog||IP Patches|
|v1.1||2019.2||(Xilinx Answer 72923)|
|v1.0 (Rev. 1)||2019.1||(Xilinx Answer 72242)|
|v1.0||2018.3||(Xilinx Answer 71806)|
|Article Number||Article Title|
|(Xilinx Answer 69403)||How do I debug the Zynq UltraScale+ VCU DDR Controller without an Example Design?|
Known and Resolved Issues
The following table provides known issues for the Zynq UltraScale+ VCU DDR Controller, starting with v1.0, initially released in Vivado 2018.3.
Note: The "Version Found" column lists the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 3: IP
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 72987)||How can I avoid the VCU DDR4 Controller IP synthesis errors when generating the output products operation in Vivado 2019.1?||v1.0 (Rev. 1)||v1.1|
Table 4: Software
|Article Number||Article Title||Version Found|
|(Xilinx Answer 71653)||PetaLinux 2018.3 - Product Update Release Notes and Known Issues||2018.3|
|11/19/2019||Added v1.1 to the Version Table and (Xilinx Answer 72987)|
|05/15/2019||Added v1.0 (Rev. 1) to the Version Table and (Xilinx Answer 69403).|