AR# 54490

Zynq UltraScale+ VCU DDR Controller - Release Notes and Known Issues for Vivado 2018.1 and later versions

描述

This answer record contains the Release Notes and Known Issues for the Zynq UltraScale+ VCU DDR Controller and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

Zynq UltraScale+ VCU DDR Controller Page:

https://www.xilinx.com/products/intellectual-property/v-vcu.html


Xilinx Forums:

Please seek technical support via the Video Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

解决方案

General Information

Supported Devices can be found in the following three locations:

Note: the Zynq UltraScale+ VCU DDR Controller is only supported for Zynq UltraScale+ VCU Applications (H.264/H.265 Video Codec Unit) in the Zynq UltraScale+ EV parts.


For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Change Log included with the core in Vivado.
  • Subsystem or IP - Click on the Change Log links below.
  • Linux - Xilinx Wiki

Table 1: Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version IP ChangelogIP Patches
v1.12019.2(Xilinx Answer 72923)
v1.0 (Rev. 1)2019.1(Xilinx Answer 72242)
v1.02018.3(Xilinx Answer 71806)

Table 2: General Guidance

The table below provides Answer Records for general guidance when using the Zynq UltraScale+ VCU DDR Controller.

Article NumberArticle Title
(Xilinx Answer 69403)How do I debug the Zynq UltraScale+ VCU DDR Controller without an Example Design?


Known and Resolved Issues

The following table provides known issues for the Zynq UltraScale+ VCU DDR Controller, starting with v1.0, initially released in Vivado 2018.3.

Note: The "Version Found" column lists the version where the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 72987)How can I avoid the VCU DDR4 Controller IP synthesis errors when generating the output products operation in Vivado 2019.1?v1.0 (Rev. 1)v1.1


Table 4: Software

Article NumberArticle TitleVersion Found
(Xilinx Answer 71653)PetaLinux 2018.3 - Product Update Release Notes and Known Issues2018.3

Revision History:

11/19/2019Added v1.1 to the Version Table and (Xilinx Answer 72987)
05/15/2019Added v1.0 (Rev. 1) to the Version Table and (Xilinx Answer 69403).
12/05/2018Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

子答复记录

相关答复记录

AR# 54490
日期 01/26/2020
状态 Active
Type 版本说明
器件
IP