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AR# 54519

LogiCORE IP Color Correction Matrix - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP Color Correction Matrix core and includes the following:

General Information
Known and Resolved Issues
Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP Color Correction Matrix core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-ccm.html

解决方案

General Information

Supported devices can be found in the following three locations:

LogiCORE IP Color Correction Matrix core Product Guide
LogiCORE IP Color Correction Matrix core IP Page
Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version	Vivado Tools Version
v6.0 (Rev. 2)	2013.3
v6.0 (Rev. 1)	2013.2
v6.0	2013.1

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP Color Correction Matrix core.

Answer Record	Title
N/A	N/A

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Color Correction Matrix core, starting with v6.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record	Title	Version Found	Version Resolved
(Xilinx Answer 57773)	Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?	v5.01.a	N/A
(Xilinx Answer 52215)	Why does my core fail timing with a Critical Warning?	v5.01.a	v6.0 (Rev. 2)
(Xilinx Answer 56274)	Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?	v6.0	v6.0 (Rev. 2)
(Xilinx Answer 55980)	Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?	v6.0	v6.0 (Rev. 1)

Revision History
10/23/2013 - Added v6.0 (Rev. 2) Version Table, (Xilinx Answer 57773) an updated Known and Resolved Issues table for 2013.3.
06/19/2013 - Added v6.0 (Rev. 1) to Version Table, (Xilinx Answer 56274), (Xilinx Answer 55980)
04/03/2013 - Initial Release

本答复记录是否对您有帮助？

链接问答记录

主要问答记录

Answer Number	问答标题	问题版本	已解决问题的版本
56852	Xilinx Multimedia, Video and Imaging Solution Center - Top Issues	N/A	N/A

子答复记录

Answer Number	问答标题	问题版本	已解决问题的版本
52215	14.3 / 2012.2 Video IP - Why does my core fail timing with a critical warning?	N/A	N/A
56274	Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?	N/A	N/A
55980	LogiCORE Video Timing Controller v5.01.a - Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?	N/A	N/A
57773	Vivado 2013.2 Multimedia Video and Imaging - Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?	N/A	N/A

AR# 54519
日期	11/10/2014
状态	Active
Type	版本说明
Tools	Vivado Design Suite - 2013.1
IP	Color Correction Matrix

AR# 54519

LogiCORE IP Color Correction Matrix - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

解决方案

链接问答记录

主要问答记录

子答复记录

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