This answer record contains the Release Notes and Known Issues for the LogiCORE IP DisplayPort core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
DisplayPort LogiCORE IP Page:
https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-displayport.html
Note: This core is obsolete.
It has been superseded by the DisplayPort RX Subsystem (Xilinx Answer 65447) and the DisplayPort TX Subsystem (Xilinx Answer 59384) and will be removed from the Vivado IP catalog in Vivado 2017.3.
The DisplayPort license also applies to the DisplayPort RX Subsystem and the DisplayPort TX Subsystem.
General Information
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v7.0 (Rev. 5) | 2017.2 |
| v7.0 (Rev. 4) | 2017.1 |
| v7.0 (Rev. 3) | 2016.4 |
| v7.0 (Rev. 2) | 2016.3 |
| v7.0 (Rev. 1) | 2016.2 |
| v7.0 | 2016.1 |
| v6.1 (Rev. 1) | 2015.4 |
| v6.1 | 2015.3 |
| v6.0 (Rev. 1) | 2015.2 |
| v6.0 | 2015.1 |
| v5.0 (Rev. 1) | 2014.4 |
| v5.0 | 2014.3 |
| v4.2 (Rev. 2) | 2014.2 |
| v4.2 (Rev. 1) | 2014.1 |
| v4.2 | 2013.4 |
| v4.1 | 2013.3 |
| v4.0 (Rev. 1) | 2013.2 |
| v4.0 | 2013.1 |
General Guidance
The table below provides answer records for general guidance when using the DisplayPort LogiCORE IP.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 67332) | If the same clock is connnected for the axi_clk and vid_clk, there are a lot of unconstrained paths appearing under the intra clock timing report for paths outside the DP IP which are driven by this clock |
| (Xilinx Answer 63907) | Does the DisplayPort IP support Fast AUX (FAUX) or Dual mode AUX? |
| (Xilinx Answer 65838) | Can the UltraScale DisplayPort Sink support sources using Spread Spectrum Clocking (SSC) when receiving at 1.62 Gbps? |
| (Xilinx Answer 65837) | What are the lnk_fwdclk_p/n clock signals that appear when targeting UltraScale devices, and how are they to be used? |
| (Xilinx Answer 65154) | What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register? |
| (Xilinx Answer 64732) | Does DisplayPort support adaptive sync or G-SYNC by NVidia? |
| (Xilinx Answer 64652) | Does the DisplayPort core or reference designs support EDID or DisplayID? |
| (Xilinx Answer 61784) | Why do I receive an error when trying to generate a bitstream that includes the DisplayPort core? |
| (Xilinx Answer 59291) | Does the DisplayPort Source DPCD Main Stream Attributes register have to match the timing of the video being input to the User Data interface? |
| (Xilinx Answer 42953) | Design Advisory Master Answer Record for LogiCORE IP DisplayPort |
Known and Resolved Issues
The following table provides known issues for the DisplayPort core, starting with v4.0, initially released in Vivado Design Suite 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
IP:
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 68892) | What is the warning message that the DisplayPort LogiCORE will be obsoleted in Vivado release 2017.2 about? | v7.0 (Rev. 4) | N/A |
| (Xilinx Answer 67433) | Why does the DisplayPort Rx driver for the DisplayPort IP and DisplayPort subsystem sometimes fail to train when using the (DP159) production silicon? | v7.0 (Rev. 1) | N/A |
| (Xilinx Answer 66371) | When Enabling "Additional Transceiver Control and Status Ports", if I close the GUI and re-open it, this option is un-checked | v6.1(Rev 1) | v7.0 |
| (Xilinx Answer 66372) | Why does the option to select Quad Pixel remain disabled when changing the number of lanes from 1 back to 4? | v6.1(Rev 1) | v7.0 |
| (Xilinx Answer 66373) | Why does selecting YCrCb 422 in the GUI not have any effect in the Hardware? | v6.1(Rev 1) | v7.0 |
| (Xilinx Answer 65795) | When should the SS Mode check box be selected? | v6.0 (Rev. 1) | v6.1 |
| (Xilinx Answer 65133) | Does XAPP1178 v2.0 run on the KC705 Rev 1.1 board? | N/A | N/A |
| (Xilinx Answer 63263) | Why do 1 and 2 lane SST modes fail to link if the DisplayPort v5.0 is generated with MST enabled? | v5.0 | v5.0 (Rev. 2) |
| (Xilinx Answer 62582) | Why are the M_VID and M_AUD values double when the GT Interface Width is set to 32-bits? | v5.0 | v5.0 (Rev.1) |
| (Xilinx Answer 61799) | GTP and GTH - Production reset DRP sequence can hang, requiring a reconfiguration to recover | v4.2 (Rev. 1) | v4.2 (Rev. 2) |
| (Xilinx Answer 38503) | Why do I get an Critical Warning saying the Reed-Solomon Decoder license is not found, and an Error in Synthesis saying a license was not found when the DisplayPort core is configured as a DisplayPort Sink? | v4.2 | N/A |
| (Xilinx Answer 61683) | Why do I get an error Name Protected error when using Cadence IUS for simulation? | v4.2 (Rev. 1) | v4.2 (Rev. 2) |
| (Xilinx Answer 60627) | Why can I not target the Automotive Aritx-7 (QArtix-7) devices? | v4.2 (Rev. 1) | N/A |
| (Xilinx Answer 59634) | Why do I see a AUX channel timeout when performing larger AUX channel transactions? | v4.0 | v4.2 (Rev. 1) |
| (Xilinx Answer 59288) | Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11 from the DisplayPort Product Guide PG064, December 18th, 2013? | v4.2 | N/A |
| (Xilinx Answer 57951) | Why do I get a Type mismatch error when simulating with Synopsys VCS H-2013.06-3? | v4.1 | N/A |
| (Xilinx Answer 57836) | Why is the Link Rate wrong when simulating with Cadence IUS 12.2-S016? | v4.1 | N/A |
| (Xilinx Answer 57399) | VESA Spec Termination Scheme Causes Corruption on the AUX State Machine | v4.0 | v4.1 |
| (Xilinx Answer 55359) | Noise on the AUX Channel causes the Core AUX State Machine to Hang | v4.0 | v4.1 |
| (Xilinx Answer 56777) | GTH Common Block Refclk is not Connected Causing DRC Error | v4.0 | v4.1 |
| (Xilinx Answer 56681) | Virtex-7 GTH - DisplayPort Core will not Synthesize Correctly in Non-Project Flow | v4.0 | v4.1 |
| (Xilinx Answer 53538) | Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input? | v3.2 | v4.0 |
| (Xilinx Answer 53539) | Why does the DisplayPort Source Stop sending audio after a reset? | v3.2 | v4.0 |
| (Xilinx Answer 56168) | Error in Simulation - Test Failed when targeting Artix-7 FPGAs | v3.2 | v4.0 (Rev 1) |
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 67274) | Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver? | v2.0 (Rev. 1) | N/A |
Revision History:
Note: This core is obsolete and has been superseded by the DisplayPort RX Subsystem and the DisplayPort TX Subsystem and will be removed from the Vivado IP catalog in Vivado 2017.3.
| 03/29/2018 | Added (Xilinx Answer 67332) |
| 06/29/2017 | Added v7.0 (Rev. 5) to Version Table. |
| 04/05/2017 | Added v7.0 (Rev. 2), v7.0 (Rev. 3) and v7.0 (Rev. 4) to Version Table, (Xilinx Answer 68892) |
| 07/14/2016 | Added v7.0 (Rev. 1) to Version Table, (Xilinx Answer 67274) and (Xilinx Answer 67433) |
| 04/06/2016 | Added v7.0 to Version Table, (Xilinx Answer 63907) |
| 11/24/2015 | Added v6.1 and v6.1 (Rev. 1) to Version Table, (Xilinx Answer 65795), (Xilinx Answer 65837), (Xilinx Answer 65838) |
| 08/06/2015 | Added (Xilinx Answer 65154) |
| 08/04/2015 | Added (Xilinx Answer 65133) |
| 06/30/2015 | Added v6.0 (Rev. 1) to Version Table and (Xilinx Answer 64652), (Xilinx Answer 64732), (Xilinx Answer 51560) |
| 04/01/2015 | Added v6.0 to Version Table |
| 01/05/2015 | Added v5.0 (Rev. 1) to Version Table and (Xilinx Answer 63263) |
| 10/22/2014 | Added (Xilinx Answer 62582) |
| 10/08/2014 | Added v5.0 to Version Table |
| 08/01/2014 | Added v4.2 (Rev. 2) to Version Table, (Xilinx Answer 61683), (Xilinx Answer 38503), (Xilinx Answer 61784), (Xilinx Answer 61799). |
| 05/13/2014 | Added (Xilinx Answer 60627) |
| 04/16/2014 | Added v4.2 (Rev. 1) to Version Table, (Xilinx Answer 59291), (Xilinx Answer 59288), (Xilinx Answer 59634), (Xilinx Answer 60227). |
| 12/18/2013 | Added v4.2 to Version Table |
| 10/23/2013 | Added v4.0 (Rev. 1) and v4.1 to Version Table, (Xilinx Answer 57836), (Xilinx Answer 57951) and updated Know and Resolved Issues table for 2013.3. |
| 09/09/2013 | Added (Xilinx Answer 55359), (Xilinx Answer 57399) |
| 07/23/2013 | Added (Xilinx Answer 56856) |
| 07/17/2013 | Added (Xilinx Answer 56777) |
| 07/03/2013 | Added (Xilinx Answer 56681) |
| 06/28/2013 | Added (Xilinx Answer 56637) |
| 05/29/2013 | Added (Xilinx Answer 56168) |
| 04/03/2013 | Initial Release |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 56852 | Xilinx Multimedia, Video and Imaging Solution Center - Top Issues | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 61625 | Video IP Example Design Landing Page | N/A | N/A |
| 59384 | DisplayPort TX Subsystem - Release Notes and Known Issues for Vivado 2015.4 and newer tool versions | N/A | N/A |
| 65447 | DisplayPort RX Subsystem - 面向 Vivado 2015.4 和更新工具版本的版本说明和已知问题 | N/A | N/A |
| 57842 | LogiCORE Video PHY Controller - 面向 Vivado 2015.4 和更新工具版本的版本说明和已知问题 | N/A | N/A |
| AR# 54522 | |
|---|---|
| 日期 | 07/17/2018 |
| 状态 | Active |
| Type | 版本说明 |
| Tools |
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| IP |
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