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AR# 54547

LogiCORE IP SMPTE UHD-SDI - Release Notes and Known Issues for the Vivado 2015.1 tool and later versions

描述

This answer record contains the Release Notes and Known Issues for the SMPTE UHD-SDI Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2015.1 and later versions.

SMPTE UHD-SDI LogiCORE IP Page:

https://www.xilinx.com/products/intellectual-property/uhd-serial-digital-interface.html

解决方案

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.


Core VersionVivado Tools VersionIP Changelog
v1.0 (Rev. 5)2017.3(Xilinx Answer 69903)
v1.0 (Rev. 4)2017.1(Xilinx Answer 69055)
v1.0 (Rev. 3)2016.3(Xilinx Answer 68021)
v1.0 (Rev. 2)2016.1(Xilinx Answer 66930)
v1.0 (Rev. 1)2015.3(Xilinx Answer 65570)
v1.02015.1


General Guidance

The table below provides Answer Records for general guidance when using the SMPTE UHD-SDI core.


Article NumberArticle Title
(Xilinx Answer 65953)How do I map RGB data to the SMPTE SD/HD/3G-SDI Core?


Known and Resolved Issues

The following table provides known issues for the SMPTE UHD-SDI core, starting with v1.0, initially released in Vivado 2015.1.

Note: The "Version Found" column lists the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 68754) Why do I see rx_mode_locked and rx_t_locked keep toggling when SDI cable isn't connectedv1.0 (Rev3)v1.0 (Rev4)
(Xilinx Answer 68794) UHD-SDI core shows Timing Errors on EDH TX paths v1.0 (Rev3)v1.0 (Rev4)
(Xilinx Answer 67742)XAPP1248 - Synthesis of the UHD-SDI core in 2016.2 is preventing the receiver from locking to the incoming video N/AN/A
(Xilinx Answer 66734)Why can I not target a Virtex UltraScale part with GTHs?v1.0v1.0 (Rev. 2)
(Xilinx Answer 56449)rx_locked occasionally asserting when no SDI cable is connectedv1.0-

Revision History:

04/04/2018Added v1.0 (Rev. 3), v1.0 (Rev. 4) and v1.0 (Rev. 5) to the Version Table
08/24/2016Added (Xilinx Answer 67742).
06/22/2016Added (Xilinx Answer 56449) and (Xilinx Answer 65953).
04/06/2016Added (Xilinx Answer 66734) and added v1.0 (Rev. 1) and v1.0 (Rev. 2) to Version Table.
04/01/2015Initial Release

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AR# 54547
日期 03/23/2018
状态 Active
Type 版本说明
IP
  • SMPTE UHD-SDI
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