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AR# 54550

LogiCORE IP MIPI D-PHY Controller - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions

Description

This answer record contains the Release Notes and Known Issues for the MIPI D-PHY Controller Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

LogiCORE MIPI D-PHY Controller Core IP Page:

https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html

解决方案

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version IP Patches
v3.12017.1
v3.0 (Rev. 1)2016.4(Xilinx Answer 68810)
v3.02016.3
v2.0 (Rev. 1)2016.2
v2.02016.1
v1.02015.3

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE MIPI D-PHY Controller core.

Article NumberArticle Title
(Xilinx Answer 67249)What is the maximum value of start-up time before High-speed data transfer?
(Xilinx Answer 66088)Are there plans to support MIPI D-PHY v1.2?

Known and Resolved Issues

The following table provides known issues for the MIPI D-PHY Controller core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 69057)Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 RX Subsystem?v3.0 (Rev. )v3.1
(Xilinx Answer 68603)Slave Mode (Shared logic in example design) D-PHY RX IP does not work when it is sharing resources with Master mode (Shared Logic in core) D-PHY RX IPv3.0 (Rev .1)v3.1
(Xilinx Answer 68603)Why does the Slave IP not work after updating to 2016.4? v3.0 (Rev. 1)3.0 (Rev. 1)N/A
(Xilinx Answer 67296)Are multi-lane use cases supported in MIPI D-PHY IP? v2.0N/A
(Xilinx Answer 67258)Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?v1.01.0v2.0

Revision History:

04/05/2017Added v3.1 to Version Table, (Xilinx Answer 68803), (Xilinx Answer 68810) and (Xilinx Answer 69057)
02/07/2017Added v2.0 (Rev.1), v3.0 and v3.0 (Rev.1) to Version Table and (Xilinx Answer 68603)
05/31/2016Added (Xilinx Answer 67258)(Xilinx Answer 67296) and (Xilinx Answer 67249)
04/06/2016Added v2.0 to Version Table
12/07/2015Added (Xilinx Answer 66088)
09/30/2015Initial Release

 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

子答复记录

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AR# 54550
日期 04/26/2017
状态 Active
Type 版本说明
器件
  • Zynq UltraScale+ MPSoC
  • Kintex UltraScale+
  • Virtex UltraScale+
IP
  • MIPI D-PHY Controller
的页面