Description

This answer record contains the Release Notes and Known Issues for the Distributed Memory Generator and includes the following:

• General Information
• Known and Resolved Issues
• Change Log History
  
• Revision History
  

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

For the latest core updates, see the product page at:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/dist_mem_gen.html

解决方案

General Information

Supported devices can be found in the following three locations:

• LogiCORE Distributed Memory Generator Product Guide.
• LogiCORE Distributed Memory Generator IP Page
• Open the Vivado tool -> IP Catalog, right-click on an IP and select "Compatible Families"

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.

General Guidance

The table below provides answer records for general guidance when using the LogiCORE Distributed Memory Generator core.

Known and Resolved Issues

The following table provides known issues for the LogiCORE Distributed Memory Generator core, starting with v8.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

• No known issue with core
  

Change Log History

 2014.3:
 * Version 8.0 (Rev. 6)
 * Reduced warnings in synthesis, no functional changes

2014.2:
 * Version 8.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

2014.1:
 * Version 8.0 (Rev. 4)
 * Internal device family name change, no functional changes

2013.4:
 * Version 8.0 (Rev. 3)
 * Added support for UltraScale devices

2013.3:
 * Version 8.0 (Rev. 2)
 * Enhanced support for IP Integrator
 * Reduced warnings in synthesis and simulation
 * Added support for Cadence IES and Synopsys VCS simulators

2013.2:
 * Version 8.0 (Rev. 1)
 * Repackaged to enable internal version management, no functional changes.

2013.1:
 * Version 8.0
 * Native Vivado Release
 * Unused port SPRA and its associated parameters removed.

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Revision History
04/03/2013 - Initial Release