This answer record contains the Release Notes and Known Issues for the 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) LogiCORE IP Pages:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Vivado Tool |
|v6.0 (Rev. 18)||2020.2|
|v6.0 (Rev. 17)||2020.1|
|v6.0 (Rev. 16)||2019.2|
|v6.0 (Rev. 15)||2019.1|
|v6.0 (Rev. 14)||2018.3|
|v6.0 (Rev. 13)||2018.2|
|v6.0 (Rev. 12)||2018.1|
|v6.0 (Rev. 11)||2017.4|
|v6.0 (Rev. 10)||2017.3|
|v6.0 (Rev. 9)||2017.2|
|v6.0 (Rev. 8)||2017.1|
|v6.0 (Rev. 7)||2016.4|
|v6.0 (Rev. 6)||2016.3|
|v6.0 (Rev. 5)||2016.2|
|v6.0 (Rev. 4)||2016.1|
|v6.0 (Rev. 3)||2015.4|
|v6.0 (Rev. 2)||2015.3|
|v6.0 (Rev. 1)||2015.2|
|v5.0 (Rev. 2)||2014.4.1|
|v5.0 (Rev. 1)||2014.4|
|v4.1 (Rev. 1)||2014.2|
|v4.1 (Rev. 1)||2014.1|
|v3.0 (Rev. 2)||(Xilinx Answer 58656)|
|v3.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE 10-Gigabit Ethernet PCS/PMA core.
|(Xilinx Answer 38279)||Ethernet IP Solution Center|
|(Xilinx Answer 55077)||Ethernet IP Cores - Design Hierarchy in Vivado|
|(Xilinx Answer 68203)||10G Ethernet PCS/PMA - 10G BASE-R gives "WARNING: [Vivado 12-1790] Evaluation License Warning:"|
|(Xilinx Answer 71188)||10-Gigabit Ethernet PCS/PMA (10GBASE-R) - UltraScale - Steps to do PRBS testing|
Known and Resolved Issues
The following table provides known issues for the 10-Gigabit Ethernet PCS/PMA core, starting with v3.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |
|N/A||Removed BUFH on the RXRECCLK_OUT for customers who want to use this for downstream logic in 7 Series to avoid Implementation issues.||v6.0 (rev .8)||v6.0 (rev .9)|
|N/A||Fixed corner case Block lock issue - Core indicates block lock is high even when the input cable is pulled||v6.0 (Rev 8)||v6.0 (Rev .9)|
|(Xilinx Answer 63704)||UltraScale GTH/GTY - How to switch to use internal PRBS pattern generator when using Asynchronous Gearbox mode||NA||NA|
|(Xilinx Answer 64103)||UltraScale - Updates to GT PROGDIVRESET logic to meet GT requirements||v6.0 (Rev. 1)||v6.0(Rev. 2)|
|(Xilinx Answer 66139)||10GBASE-KR - UltraScale - TXOUTCLK frequency will change between normal operation and AN/LT and should not be shared between multiple cores||NA||NA|
|(Xilinx Answer 64123)||UltraScale GTH - 10GBASEKR - Auto-Negotiation/Link training Occasionally takes extra time to complete||v5.0||See AR|
|(Xilinx Answer 63961)||UltraScale GTH - 10GBASEKR - Attribute Update needed if using Auto-Negotiation||v5.0||v6.0|
|(Xilinx Answer 59911)||GTRXRESET is required if RX Serial Data is lost||v4.1||v4.1 (Rev. 1)|
|(Xilinx Answer 59910)||PMA or PCS Reset during MDIO transaction could result in missed operation||v4.1||v4.1 (Rev. 1)|
|(Xilinx Answer 59904)||10GBASE-KR - Verilog - Auto Negotiation - Configuration Vector - Link Training does not start automatically||v4.1||v4.1 (Rev. 1)|
|(Xilinx Answer 58069)||Configuration Vector - 125us timer not initialized correctly in example design||v2.6||v4.1|
|(Xilinx Answer 57987)||10GBASE-KR Support||NA||NA|
|(Xilinx Answer 58660)||Update needed to Synchronizer logic, block lock sometimes does not go high for 10GBASE-KR||v3.0||v3.0 (Rev 2)|
|(Xilinx Answer 58412)||Update to RXRESETTIME transceiver CDR lock timer values||v3.0||v3.0 (Rev 2)|
|(Xilinx Answer 58659)||Period constraint update for the dclk in the Out-of-Context XDC file||v3.0 (Rev. 1)||v3.0 (Rev 2)|
|(Xilinx Answer 57847)||Update to RX Elastic Buffer to avoid possible underflow, latency increased||v2.6||v4.0|
|(Xilinx Answer 56332)||Virtex-7 GTH - QPLL Attribute Updates for Production Silicon||v3.0||v4.0|
|(Xilinx Answer 55676)||7 Series - PRBS31 - DRP access to the GTX transceiver PRBS31 error counter could interfere with MDIO interface if used||v3.0||v3.0 (Rev. 1)|
|(Xilinx Answer 55728)||7 Series - PRBS31 - Core DRP access to the GTH transceiver PRBS31 error counter should not be used||v3.0||v3.0 (Rev. 1)|
|(Xilinx Answer 55235)||10GBASE-KR - Auto Negotiation with no FEC - Marginal timing seen||v3.0||v3.0 (Rev. 1)|
|(Xilinx Answer 52531)||7 Series - Timing errors sometimes seen on path to and from Transceiver||v2.5||v3.0 (Rev. 1)|
|(Xilinx Answer 53443)||7 Series - TX FAULT and Signal Detect inputs from SFP do not need to connected to both RX and TX reset logic||v2.6||v3.0|
|(Xilinx Answer 52611)||7 Series - GTH Transceivers - Updated RXCDR attribute for targeting GES silicon||v2.6||v3.0|
|12/09/2013||Added 58656, 58659, and 58660|