AR# 54699


Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - dont_touch, full_case, gated_clock, shreg_extract


This answer record describes the Vivado Synthesis Attributes, dont_touch, full_case, gated_clock, shreg_extract, and also provides coding examples for them. 

The coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. 

Please refer to the header in each source file for the Synthesis attributes covered in each example.



The dont_touch attribute works in the same way as the "keep" and "keep hierarchy" attributes. 

Its function is to prevent logic optimization of either signals or hierarchical blocks and forward annotate the netlist to place and route.

Verilog Example
(* dont_touch = "{true|false}" *) <signal_name>;

VHDL Example
attribute dont_touch : string;
attribute dont_touch of <signal_name> : signal is "{true|false}";

 FULL_CASE (Verilog only)

The full_case attribute can be used to instruct Vivado Synthesis that all possible values have been specified in the statements. 

If case values are specified, extra logic for case values is not created by Vivado Synthesis. The attribute can only be controlled through RTL.

Verilog Example

        (* full_case *) 
        case (SELECT)
            3'b001 : Q1 <= A[0];
            3'b011 : Q1 <= A[1];
            3'b110 : Q1 <= A[2];



The gated_clock attribute purpose is to convert clock gating logic to flop enable. 

This makes use of the flip flop clock enables and dedicated clock routing. 

Vivado synthesis allows the conversion of gated clocks. The two items to use to perform this conversion are:

  • A switch (-gated_clock_conversion) in the GUI, that instructs the tool to attempt the conversion.
  • The RTL attribute that instructs the tool about which signal in the gated logic is the clock.

Verilog Example

(* gated_clock = "{true|false}" *)  input clk_a;

VHDL Example

    Port ( clk_a : in STD_LOGIC;
           en        : in STD_LOGIC;
end top;

architecture Behavioral of top is

signal gclk_a : STD_LOGIC;

attribute gated_clock : string;
attribute gated_clock of clk_a : signal is "{true|false}"; 

gclk_a <= clk_a AND en;



The shreg_extract attribute allows Vivado Synthesis to enable the extraction of shift registers when applicable. Applicable values are "true" and "false"

Verilog Example

placed before register

(* shreg_extract = "{yes|no}" *) reg [n:0] <reg_name>;

VHDL Example

attribute shreg_extract : string;
attribute shreg_extract of shreg : signal is "{yes|no}";


Attribute NameHDL Files
  • dont_touch.v
  • dont_touch.vhd
  • full_case.v
  • gated_clock.v
  • gated_clock.vhd
  • shreg_extract.v
  • shreg_extract.vhd


文件名 文件大小 File Type 4 KB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
55160 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support N/A N/A
AR# 54699
日期 03/31/2020
状态 Active
Type 解决方案中心
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