Phase 7.1.2 Build Placer Device | Checksum: 372f7a77
Time (s): elapsed = 00:00:04 . Memory (MB): peak = 1128.172 ; gain = 119.789
ERROR: [Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk1] >
_inst1 (BUFG.O) is locked to BUFGCTRL_X0Y86 (in SLR 2)
_inst2 (BUFG.I) is locked to BUFGCTRL_X0Y68 (in SLR 2)
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_gclkio_bufg
Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
as the BUFG
clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y426 (in SLR 2)
_inst1 (BUFG.I) is locked to BUFGCTRL_X0Y86 (in SLR 2)
Clock Rule: rule_multi_slr_bufg
Rule Description: For a multi-SLR device, a maximum of one BUFG at same relative position in different
SLRs can be used, that is two BUFG sites whose Y-index differs by a multiple of 32 cannot be used
at the same time
_inst2 (BUFG.O) is locked to BUFGCTRL_X0Y68 (in SLR 2)
Resolution: A dedicated routing path between the two BUFGs can be used if they are placed in cyclically adjacent BUFG sites and both are in the same half (TOP/BOTTOM) side of an SLR.