AR# 55134

MIG 7 Series - All interfaces have pll_locked and not mmcm_locked tied to their reset structure

描述

Version Found: v1.5
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)

All MIG 7 Series interfaces use a Phase Locked Loop (PLL) with its LOCKED signals tied into the reset structure.

An additional MMCM was added starting with the MIG 7 series v1.5 (See (Xilinx Answer 47043)), but the LOCKED signal was not tied into the reset structure.

解决方案

This is not expected to cause failures within the MIG designs but can be corrected by making the following changes within infrastructure.v:

change:

assign rst_tmp_phaser_ref = sys_rst_act_hi | ~pll_locked_i | ~iodelay_ctrl_rdy;

to:

assign rst_tmp_phaser_ref = sys_rst_act_hi | ~mmcm_locked | ~iodelay_ctrl_rdy;

Revision History
04/03/2013 - Initial Release

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Answer Number	问答标题	问题版本	已解决问题的版本
54025	MIG 7 Series - IP Release Notes and Known Issues for Vivado	N/A	N/A

AR# 55134
日期	08/18/2014
状态	Active
Type	已知问题
器件	Artix-7 Kintex-7 Virtex-7
IP	MIG 7 Series

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AR# 55134

MIG 7 Series - All interfaces have pll_locked and not mmcm_locked tied to their reset structure

描述

解决方案

链接问答记录

主要问答记录