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AR# 55225

Vivado Synthesis - How can I avoid longer constraint validation times during early development cycles?

描述

How can I avoid longer constraint validation times during early development cycles?

解决方案

The Vivado flow does constraint validation by default when synthesis is called. The constraint validation time can take longer during synthesis stage. Xilinx recommends that users not provide XDC constraints during early RTL development and cleanup stages. These can be included later when timing closure of implementation is being worked on.

Work is in progress to reduce the long constraint validation times permanently in future releases.

AR# 55225
日期 06/19/2013
状态 Active
Type 已知问题
Tools
  • Vivado Design Suite
的页面