AR# 55297

描述

When implementing the SEM IP targeting Artix or Zynq devices with a 100 MHz ICAP clock, setup time violations might occur between a RAMB18E1 in the controller and a register in the example design MON shim.

解决方案

1. Identify the failing path in the timing report.
2. Add a constraint to overconstrain this path to 9.75 ns.
3. Re-implement the design.
4. Verify in the timing report that the design meets timing for 100 MHz performance.

Example

Source:               example_controller/U0/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw1/fw1_1024x18 (RAM)

Destination:       example_mon/example_mon_fifo_tx/augend_3 (FF)

INST "example_controller/U0/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw1/fw1_1024x18" TPSYNC = RAM_SRC ;

TIMESPEC "TS_MAXDELAY" = FROM "RAM_SRC" TO FFS(*) 9750 ps ;

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