When implementing the SEM IP targeting Artix or Zynq devices with a 100 MHz ICAP clock, setup time violations might occur between a RAMB18E1 in the controller and a register in the example design MON shim.
Example
Source: example_controller/U0/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw1/fw1_1024x18 (RAM)
Destination: example_mon/example_mon_fifo_tx/augend_3 (FF)
INST "example_controller/U0/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw1/fw1_1024x18" TPSYNC = RAM_SRC ;
TIMESPEC "TS_MAXDELAY" = FROM "RAM_SRC" TO FFS(*) 9750 ps ;
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
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44541 | Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4 | N/A | N/A |
AR# 55297 | |
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日期 | 06/03/2013 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools | |
IP |