描述

Version Resolved and other Known Issues: See (Xilinx Answer 54646)

When using the AXI Bridge for PCI Express core, designs might fail to meet timing on the following devices:

• Artix-7 Devices
• Smaller Zynq Devices
  

解决方案

For Vivado 2015.3

In case of timing violation, set opt_design to "Explore Sequential Area".

For Vivado 2014.4

In cases of timing violations with the default implementation strategy, re-implement the design by selecting the "performance_ExplorePostRoutePhysOpt" implementation strategy.

set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_name]

For Vivado 2013.4 - Vivado 2014.3

To eliminate timing violations, set the properties below:

For x1g1_128bit configuration:

set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION sequential [get_runs synth_name]
set_property strategy Performance_Retiming [get_runs impl_name]
set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_name]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_name]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_name]

For x1g2_128bit configuration:

set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION sequential [get_runs synth_name]
set_property strategy Performance_Retiming [get_runs impl_name]

For x4g2_128bit configuration:

set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION sequential [get_runs synth_name]
set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_name]

set_property strategy Performance_Explore [get_runs impl_name]

Note: "Version Found" refers to the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

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