AR# 55739


LogiCORE IP Serial RapidIO Gen2 v2.0 - No packets transferred in example design simulation


Version Found: 2.0
Version Resolved and other Known Issues for v2.0 core: See (Xilinx Answer 54648)

When simulating the LogiCORE IP Serial RapidIO Gen2 v2.0 example design, the simulator reports 'Test Passed,' but no packets are transferred between the core and the test bench.


This is a known issue to be fixed in the next release of the core.

To work around the issue in this release of the core, install the SRIO Gen2 v2.0 Rev1 patch that is available in (Xilinx Answer 55737).

Revision History
05/02/2013 - Initial release



Answer Number 问答标题 问题版本 已解决问题的版本
54648 LogiCORE IP Serial RapidIO Gen2 Core - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 55739
日期 11/05/2013
状态 Active
Type 已知问题
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