We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56009

FIFO Generator v9.3 - How to run Structural Simulation for built-in FIFO in the Vivado tool with standalone and multiple instances of FIFO Generator core in the design


The built-in FIFO simulation from the Vivado tool generates an error below while trying to run behavioral simulation for the FIFO in Vivado:

Failure: FAILURE: Use of behavioral models for Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation.

There is no direct option in the Vivado tool to generate a Structural Simulation model in Vivado.


To run Structural Simulation of the built-in FIFO, you will need to create a structural model.

  1. In the Vivado GUI, Set IP as Top, run synthesis.
  2. After synthesis is complete, you can write out a back annotated simulation model for the IP by running the following commands from the TCL console accessible from the Vivado GUI.
    • write_verilog -mode funcsim <corename>.v (for Verilog)
    • write_vhdl -mode funcsim <corename>.vhd (for VHDL)
  3. Add the model as a simulation only source for the flow to simulate the IP.

For the design that has multiple instances of FIFO Generator, you need to run the rename_ref command before running the write commands.
The rename_ref command is a must for uniquify the FIFO instances, otherwise simulation may fail with some other errors.

You can use the below proc for multiple instances of built-in FIFO core in a design:

proc gen_synth_net { ip_file ip_dir part_name } {
   create_project -in_memory -part $part_name
   set ip_name [file rootname [file tail $ip_file]]
   read_ip $ip_file
   synth_design -mode out_of_context -top $ip_name
   rename_ref -prefix_all ${ip_name}
   write_verilog -mode funcsim -force -file $ip_dir/$ip_name/${ip_name}_post_synth.v
   puts "Wrote Verilog simulation for $ip_name"
   return 0
AR# 56009
日期 01/08/2014
状态 Active
Type 综合文章
  • FPGA Device Families
  • Vivado Design Suite - 2012.4
  • FIFO Generator