Version Found: v1.08.a
Version Resolved and other Known Issues for v1.08.a: See (Xilinx Answer 44969)
When AXI Memory Mapped to PCI Express core is configured with C_S_AXI_ID_WIDTH = 13 or higher, synthesis will fail with the following error message:
ERROR:HDLCompiler:1318 - "D:/Xilinx/14.6/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_v1_08_a/hdl/vhdl/axi_slave_read.vhd" Line 570: Left bound value <14> of slice is out of range [12:0] of array <zeros>
The RTL is hard coded with a constant that is only 12:0 bits wide. To fix the issue, follow the steps below:
1) Make the PCIe core local by right-clicking the core and choosing Make this IP core local
2) Navigate into <your design> directory -> pcores -> axi_pcie_v1_08_a -> hdl -> vhdl folder, and open axi_slave_read.vhd
3) Search for constant ZEROS. Change it from:
constant ZEROS : std_logic_vector(12 downto 0) := "0000000000000";
constant ZEROS : std_logic_vector(13 downto 0) := "00000000000000";
This extends the vector by one more bit (or however many bits you may have on the C_S_AXI_ID_WIDTH parameter).
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
8/26/2013 - Initial Release