AR# 57279

MIG 7 Series DDR3 RDIMM - Clock Driver Enable settings for RC1 may cause initialization failures

描述

Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series DDR3 RDIMM designs set the RC1 Clock Driver Enable control word to enable or disable the four output clocks in the for the SSTE32882 register chip located on the RDIMM. For single rank and dual rank designs, MIG only enables two clocks to conserve power. However, for the Micron MT9JSF25672PZ, the default clock drivers enabled are set incorrectly and may cause initialization failures in hardware.

解决方案

The SPD module on the RDIMM can be read to determine which specific clock outputs are used and should be enabled, but MIG does not have the capability to read from the SPD so to resolve this issue all 4 clock drivers are enabled. 

To work around the issue, the following RTL changes can be made inside mig_7series_v2_0_ddr_phy_init.v:

localparam REG_RC1 = 8'b00000001;

Revision History:
08/28/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 57279
日期 09/03/2013
状态 Active
Type 已知问题
器件
IP