UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57965

2013.2 Vivado HLS - Some DSP cores available for 7 series FPGA (Virtex-7) are not available for Virtex-6 FPGA

描述

Some DSP cores available for 7 series FPGA (Virtex-7) are not available for Virtex-6 FPGA, however, not all DSP cores are affected.

When directives and designs targeting Virtex-7 FPGA are changed to Virtex-6 FPGA, they stop working and errors of the "core not found" are returned.

#pragma HLS RESOURCE variable=x core=AddSub_DSP
@E [SYN-106] Invalid resource directive (top.cpp:123) in function 'foo': Cannot find core 'AddSub_DSP'.

Since the DSP slices (DSP48E1) are the same in both architectures, why is this happening?

解决方案

Some 7 series DSP cores have been added recently and will not be back-ported to older architectures.

If a simple work-around for Virtex-6 FPGA is needed, you can generate the IP for Virtex-7 FPGA and edit the RTL to target Virtex-6 FPGA in the DSP modules. However, other issues can arise from doing this.

A list of the supported cores can be generated per architecture with the attached TCL script and generate the table below.

This TCL script is provided as an example only.

Table of supported cores for architectures : Spartan-3 | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7
|  1 | AddSub            | X | X | X | X | X |
|  2 | AddSub_DSP        | - | - | - | - | X |
|  3 | AddSubnS          | X | X | X | X | X |
|  4 | AXI4LiteS         | X | X | X | X | X |
|  5 | AXI4M             | X | X | X | X | X |
|  6 | AXI4Stream        | X | X | X | X | X |
|  7 | DAddSub_fulldsp   | X | - | X | X | X |
|  8 | DAddSub_nodsp     | X | X | X | X | X |
|  9 | DDiv              | X | X | X | X | X |
| 10 | DExp_fulldsp      | - | - | - | - | X |
| 11 | DExp_meddsp       | - | - | - | - | X |
| 12 | DExp_nodsp        | - | - | - | - | X |
| 13 | DivnS             | X | X | X | X | X |
| 14 | DLog_fulldsp      | - | - | - | X | X |
| 15 | DLog_meddsp       | - | - | - | X | X |
| 16 | DLog_nodsp        | - | - | - | X | X |
| 17 | DMul_fulldsp      | X | X | X | X | X |
| 18 | DMul_maxdsp       | X | X | X | X | X |
| 19 | DMul_meddsp       | X | - | X | X | X |
| 20 | DMul_nodsp        | X | X | X | X | X |
| 21 | DRecip            | - | X | - | X | X |
| 22 | DRSqrt            | - | - | - | X | X |
| 23 | DSqrt             | X | X | X | X | X |
| 24 | FAddSub_fulldsp   | X | - | X | X | X |
| 25 | FAddSub_nodsp     | X | X | X | X | X |
| 26 | FDiv              | X | X | X | X | X |
| 27 | FExp_fulldsp      | - | - | - | - | X |
| 28 | FExp_meddsp       | - | - | - | - | X |
| 29 | FExp_nodsp        | - | - | - | - | X |
| 30 | FIFO              | X | X | X | X | X |
| 31 | FIFO_BRAM         | X | X | X | X | X |
| 32 | FIFO_LUTRAM       | X | X | X | X | X |
| 33 | FIFO_SRL          | X | X | X | X | X |
| 34 | FLog_fulldsp      | - | - | - | X | X |
| 35 | FLog_meddsp       | - | - | - | X | X |
| 36 | FLog_nodsp        | - | - | - | X | X |
| 37 | FMul_fulldsp      | X | X | X | X | X |
| 38 | FMul_maxdsp       | X | X | X | X | X |
| 39 | FMul_meddsp       | X | X | X | X | X |
| 40 | FMul_nodsp        | X | X | X | X | X |
| 41 | FRecip_fulldsp    | - | X | - | X | X |
| 42 | FRecip_nodsp      | - | X | - | X | X |
| 43 | FRSqrt_fulldsp    | - | X | - | X | X |
| 44 | FRSqrt_nodsp      | - | X | - | X | X |
| 45 | FSqrt             | X | X | X | X | X |
| 46 | Mul               | X | X | X | X | X |
| 47 | Mul2S             | X | X | X | X | X |
| 48 | Mul3S             | X | X | X | X | X |
| 49 | Mul4S             | X | X | X | X | X |
| 50 | Mul5S             | X | X | X | X | X |
| 51 | Mul6S             | X | X | X | X | X |
| 52 | MulnS             | X | X | X | X | X |
| 53 | RAM_1P            | X | X | X | X | X |
| 54 | RAM_1P_BRAM       | X | X | X | X | X |
| 55 | RAM_1P_LUTRAM     | X | X | X | X | X |
| 56 | RAM_2P            | X | X | X | X | X |
| 57 | RAM_2P_1S         | X | X | X | X | X |
| 58 | RAM_2P_BRAM       | X | X | X | X | X |
| 59 | RAM_2P_LUTRAM     | X | X | X | X | X |
| 60 | RAM_T2P_BRAM      | X | X | X | X | X |
| 61 | ROM_1P            | X | X | X | X | X |
| 62 | ROM_1P_1S         | X | X | X | X | X |
| 63 | ROM_1P_BRAM       | X | X | X | X | X |
| 64 | ROM_1P_LUTRAM     | X | X | X | X | X |
| 65 | ROM_2P            | X | X | X | X | X |
| 66 | ROM_2P_BRAM       | X | X | X | X | X |
| 67 | ROM_2P_LUTRAM     | X | X | X | X | X |
| 68 | Vivado_FFT        | X | X | X | X | X |

附件

文件名 文件大小 File Type
list_core_table_cols2.tcl 1 KB TCL

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47429 Xilinx Vivado HLS Solution Center - Top Issues N/A N/A
AR# 57965
日期 10/23/2013
状态 Active
Type 文档变更
Tools
的页面