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AR# 58103

Vivado Hardware Tools - Clock Selection Enhancement

描述

Designs that include Vivado ILA cores and multiple available clocks will select the XSDB Master clock automatically. This behavior does not allow for users to account for clocks that may be stopped by the design. The MIG IP core in the 2013.3 version of Vivado can encounter this issue when paired with debug cores.

解决方案

Manual selection of the XSDB Master clock will be possible in a future revision of the tools.
AR# 58103
日期 10/31/2013
状态 Active
Type 综合文章
器件
Tools
的页面