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AR# 58662

Artix-7 FPGA AC701 Evaluation Kit - UG952 (v1.2), DDR3 Interface Banks Information


In the AC701 Evaluation Board for the Artix-7 FPGA User Guide v1.2 (UG952), it states the following on page 12:

"The DDR3 interface is implemented across I/O banks 32, 33, 34. Each bank is a 1.5V high-performance (HP) bank."

Is this accurate?


The XC7A200T does not have HP banks, so this statement in UG952 (v1.2) is not accurate.

It should read:

"The DDR3 interface is implemented across I/O banks 33, 34, and 35. Each bank is a 1.5V high-range (HR) bank."

This is corrected in v1.3 of (UG952).

AR# 58662
日期 03/11/2015
状态 Active
Type 综合文章
Boards & Kits