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AR# 59284

MIG 7 Series DDR3/DDR2 - Manual Window Check feature does not work with VIO 2.0

描述

Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

The MIG 7 series example design has the ability to verify read and write window margin on a per-byte basis when the debug signals are enabled. This can be done using the automated flow or by manually incrementing and decrementing the PHASER taps to verify how much window margin is available. When using the manual flow, the user is required to send a single pulse event to the dbg_po/pi_f_inc/dec VIO signals to increment or decrement the taps once. However, the VIO 2.0 cores do not support single event pulse, so when the dbg_po/pi_f_inc/dec signals are toggled, the taps max out and the user is unable to accurately detect the edges of the data window.

解决方案

This issue only affects the manual flow, so continue to use the automated flow to verify the read and write window margin on a per-byte basis.

Revision History
1/31/2014 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 59284
日期 01/31/2014
状态 Active
Type 已知问题
器件
IP
的页面