AR# 59375

7 Series Integrated Block Wrapper for PCI Express v3.0 - VCS/Modelsim simulation fails when simulating the core generated for Artix-7 device targeting VHDL

描述

Version Found: v3.0
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

When compiling libraries for VCS with the following command and running the script generated with export_simulation to simulate the example design generated with 7 Series Integrated Block Wrapper for PCI Express v3.0 core, for Artix-7 devices,
it runs into an error message:

compile_simlib -simulator vcs_mx -family artix7 -directory ../VCS_LIB_DIRECTORY
export_simulation -simulator vcs_mx -directory SCRIPT -force -lib_map_path ../VCS_LIB_DIRECTORY/

The reported error message is as follows:

Error - [URMI] Unresolved modules
*/data/verilog/src/unisims/GTXE2_CHANNEL.v, 3191
"B_GXE2_CHANNEL_INST"
Module definition of above instance is not found in the design.

Note: The issue is also seen with Modelsim.

解决方案

This is a known issue to be fixed in a future release of the core.

To work around this issue, compile the libraries with " -family all" instead of " -family artix7" as shown below:

compile_simlib -simulator vcs_mx -family all -directory ../VCS_LIB_DIRECTORY

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
02/12/2014 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54643 7 Series Integrated Block for PCI Express — Vivado 2013.1 及更新工具版本的发布说明及已知问题 N/A N/A
AR# 59375
日期 04/18/2014
状态 Active
Type 已知问题
器件
IP