AR# 59504

AXI Ethernet Core v6.0 and earlier - Occasionally PHY_RESET_N is not de-asserted after powerup

描述

In AXI Ethernet v2.01.a, it was found that PHY_RESET_N occasionally would not be de-asserted in a design where the GTX clock is driven by a DCM/MMCM and/or is not stable for anytime after configuration.  An SRL32 is used as a counter for this reset logic and the contents of the counter could be corrupted if the clock is not stable. 

解决方案

This is planned to be fixed in AXI Ethernet v6.1, scheduled to be released in Vivado 2014.1.  

If using Vivado, please contact Xilinx Support if a workaround is needed before the 2014.1 update.

If using v2_xx.xor v3_xx.x in EDK  this logic can be edited and the core regenerated.\EDK\hw\XilinxProcessorIPLib\pcores\axi_ethernet_\hdl\vhdl\reset_combiner.vhd make the following changes:

1) Add the following signals:
signal srl32_1_reg                : std_logic_vector (30 downto 0); -- depth is 31
signal srl32_2_reg                : std_logic_vector (18 downto 0); -- depth is 19

2) Change:
  GTX_RESET_PULSE : process (GTX_CLK_125MHZ)
  begin
    if (GTX_CLK_125MHZ'event and GTX_CLK_125MHZ = '1') then
      if (s_axi_areset = '1') then
到:
  GTX_RESET_PULSE : process (GTX_CLK_125MHZ)
  begin
    if (GTX_CLK_125MHZ'event and GTX_CLK_125MHZ = '1') then
      if (saxiResetGtxDomain = '1') then

3) Comment out SRLC32E_1 and SRLC32E_2 SRL instantiations.

4) Add the following slice based counter logic to replace the SRLs:

  SRLC32E_1 : process(GTX_CLK_125MHZ)
  begin
      if (GTX_CLK_125MHZ'event and GTX_CLK_125MHZ = '1') then
          if (saxiResetGtxDomain = '1') then     
              srl32_1_reg <= "0000000000000000000000000000001";
          else
              srl32_1_reg <= srl32_1_reg(29 downto 0) & srl32_1_reg(30);
          end if;
      end if;
  end process;

  SRLC32E_2 : process(GTX_CLK_125MHZ)
  begin
      if (GTX_CLK_125MHZ'event and GTX_CLK_125MHZ = '1') then
          if (saxiResetGtxDomain = '1') then                
              srl32_2_reg <= "0000000000000000001";
          elsif(srl32_1_reg(30)='1') then
              srl32_2_reg <= srl32_2_reg(17 downto 0) & srl32_2_reg(18);
          end if;
      end if;
  end process;
   


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AR# 59504
日期 06/08/2020
状态 活跃
Type 一般类
IP