AR# 59515

MIG 7 Series - Vivado does not generate the correct VHDL instantiation template

描述

Version Found: MIG 7 Series v2.0 Rev 2
Version Resolved: See (Xilinx Answer 54025)

The MIG 7 Series VHDL instantiation template file (.VHO) is not generated correctly. 

The syntax is not correct and is missing the component declaration.

解决方案

To work around the issue, open the example design and view the instantiation of the MIG core in the example design for reference.

Revision History
03/04/2014 - Initial release

AR# 59515
日期 04/15/2014
状态 Active
Type 已知问题
器件
Tools
IP