AR# 60181

UltraScale DDR4/DDR3 - Timing violations can occur at higher data rates

描述

Version Found: DDR4 v5.0, DDR3 v5.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, see (Xilinx Answer 69036) for DDR3

At the top supported data rates for each speed grade, timing violations might be seen within the MIG UltraScale DDR4/DDR3 cores.

解决方案

These timing violations are currently under analysis.

Improvements will be made continually in the next two releases and will be resolved with the Vivado 2014.3 release.

Revision History:

04/16/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 60181
日期 02/02/2018
状态 Active
Type 已知问题
器件
Tools
IP