This Release Note is for the Clocking Wizard v5.1 Rev 2, released in Vivado 2014.1, which contains the following:
The Clocking Wizard v5.1 rev 2 supports the UltraScale, 7 series FPGAs and Zynq devices.
New Features in v5.1 Rev2
Added UltraScale FPGA device support.
Updated to use inverted output CLKOUTB 0-3 of clocking primitive based on requested 180 phase w.r.t previous clockck.
Bug Fixes in v5.1 Rev2
Known Issues in v5.1 Rev2
Clocking Wizard v5.1 core in 2014.1 may fail with "ERROR: Freq of CLK_OUT is not correct".
This is due to the period variation of more than +/- 100 ps on CLK_OUT in simulation. This is a simulation model issue.
Workaround 1: Use a custom test bench instead of the example test bench provided along with the core.
Workaround 2: User may try using QuestaSim if the simulation fails in XSIM when using the example test bench. There is no workaround if the QuestaSim simulation itself is failing.
15/04/14 - Initial Release