AR# 60958


MIG 7 Series - Fails to verify valid pinout during "Verify Pin Changes and Update Design" with the error "Memory interface signals should be selected in consecutive banks


Version Found: MIG 7 Series v2.0 Rev 3
Version Resolved: See (Xilinx Answer 54025)

A MIG 7 Series core can span a maximum of 3 consecutive banks (i.e. banks 9, 10, 11).

Even if this requirement is followed the following error message may be seen during Verify Pin Out in the MIG GUI:

ERROR : Memory interface signals should be selected in consecutive banks. Banks selected: 9, 11, 10.
To bypass this error and proceed further for design generation, refer to AR #43481.
INFO : Cannot verify further unless the existing errors are resolved.


This is an error in the verification algorithm and can be safely ignored.

To bypass the error please proceed to (Xilinx Answer 43481).

Revision History

06/09/2014 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
43481 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules N/A N/A
AR# 60958
日期 06/06/2014
状态 Active
Type 已知问题
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