AR# 61129

UltraScale DDR3 - "ERROR: tCK(avg) minimum violation"

描述

Version Found: DDR3 v5.0 Rev1

Version Resolved: See (Xilinx Answer 69036)

When simulating MIG UltraScale DDR3 designs the following error messages might be seen even though the simulation "TEST PASSED":

# sim_tb_top.mem_model_x16.mem.memModel[0].u_ddr3_x16.main: at time 4907688.0 ps ERROR: tCK(avg) minimum violation by 2.888672 ps.
# sim_tb_top.mem_model_x16.mem.memModel[1].u_ddr3_x16.main: at time 4907688.0 ps ERROR: tCK(avg) minimum violation by 2.888672 ps.
# sim_tb_top.mem_model_x16.mem.memModel[2].u_ddr3_x16.main: at time 4907688.0 ps ERROR: tCK(avg) minimum violation by 2.888672 ps.
# sim_tb_top.mem_model_x16.mem.memModel[3].u_ddr3_x16.main: at time 4907688.0 ps ERROR: tCK(avg) minimum violation by 2.888672 ps.

解决方案

The tCK(avg) violation reported by the DDR3 memory model is a result of the actual CK/CK# clock period being different than the clock period specified during IP generation.

This is an error with the clocking wizard that calculates the available input clock periods available and will be addressed in a future release.

To work around this issue the MIG IP must be regenerated with a different input clock period specified.

Revision History:

06/13/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 61129
日期 01/02/2018
状态 Active
Type 已知问题
器件
Tools
IP