Version Found: DDR3 v5.0 Rev1
Version Resolved: See (Xilinx Answer 69036)
When simulating MIG UltraScale DDR3 designs the following error messages might be seen even though the simulation "TEST PASSED":
The tCK(avg) violation reported by the DDR3 memory model is a result of the actual CK/CK# clock period being different than the clock period specified during IP generation.
This is an error with the clocking wizard that calculates the available input clock periods available and will be addressed in a future release.
To work around this issue the MIG IP must be regenerated with a different input clock period specified.
06/13/2014 - Initial Release