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AR# 61384

2014.2 AXI QSPI - Mismatch between RTL behavior and documentation of the Read transaction of the AXI QSPI

描述

The file axi_quad_spi_v3_0\hdl\src\vhdl\qspi_core_interface.vhd contains the following code:
 
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
  IP2Bus_Error_1          <= intr_ip2bus_error   or
                           rst_ip2bus_error      or
                           transmit_ip2bus_error or
                           receive_ip2bus_error;
 
This conflicts with the statement in the user guide LogiCORE IP AXI Quad Serial Peripheral Interface (SPI) v3.0 Product Guide:
 
"The receive FIFO is a read-only buffer.
If an attempt is made to read an empty receive register or FIFO, the AXI read transaction completes successfully with undefined data."
 
Is the documentation incorrect, or is the RTL behavior incorrect?

解决方案

According to the RTL there is an error expected when an empty FIFO is read.
 
This is an expected behavior as tested in Simulation as well as on Hardware.
 
The line mentioned in the Product Guide, "The receive FIFO is a read-only buffer. If an attempt is made to read an empty receive register or FIFO, the AXI read transaction completes successfully with undefined data." is incorrect.
 
AR# 61384
日期 05/05/2015
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • Vivado Design Suite - 2014.2
IP
  • AXI Serial Peripheral Interface
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