AR# 61651


7 Series Integrated Block for PCI Express v3.0 (Rev2) - Secondary Bus Reset bit functionality in RP mode does not work as expected


Version Found: v3.0 (Rev2)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

This issue arises when the 7 Series Integrated Block for PCI Express v3.0 (Rev2) core is configured in Root Port (RP) mode and Secondary Bus Reset bit is set in Bridge Control Register.

The Link Training and Status State Machine (LTSSM) should stay in a 'Hot Reset' state, but instead goes into a 'Timeout to Detect' state after 2ms timeout. 


As per the PCI Express Specification, after setting Secondary Bus Reset in Bridge Control Register in RP configuration, all lanes in the configured Link should continue to transmit TS1 with the Hot Reset bit set and the RP LTSSM should not come out of Hot Reset.

The above issue is a known issue and is not currently planned to be fixed.

If this could be an issue in your system, instead of holding in 'Hot Reset', direct the RP LTSSM to a 'Disabled' state by setting the 'Link Disable' bit in the Link Control Register.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
08/26/2014 - Initial Release
AR# 61651
日期 08/25/2014
状态 Active
Type 已知问题
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