See (Xilinx Answer 54025)
MIG only supports behavioral simulations and does not support structural (i.e. gate-level) simulations of any kind.
However, when using Out-Of-Context (OOC) flow the <IP_name>_funcsim.v/.vhdl output products are still generated.
This can be misleading and will cause simulation failures if the <IP_name>_funcsim.v/.vhdl model is used.