AR# 62322


MIG 7-series QDR/RLD memory debug signals don't show bit wise assignment on Vivado 2013.3


Due to Vivado Hardware Manager change in the handling of ILA and debug ports, debug ports now show the bus name only.


There has been a change in the way the debug signals are displayed in Vivado Hardware Manager.
In the Hardware Manager ILA window, Instead of the individual signals described in the UG586 it will show an entire bus in the ILA probes.
To work around this, refer back to RTL signal assignment to expand the individual probes in the ILA waveform window.
This issue is to be resolved by Vivado 2014.4
 ILA_naming_Issue .PNG





Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 62322
日期 10/15/2014
状态 Active
Type 综合文章
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