AR# 63022

UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware

描述

Version Found: DDR4 v6.1, DDR3 v6.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

Dual Rank DIMMs that use address mirroring require specific RTL within the MIG IP to support the address mirror between ranks.

While MIG generates designs for dual rank DIMMs that use address mirroring, the RTL is not modified to support the mirroring and as a result the addressing is incorrect.

This will cause hardware failures.

解决方案

Until this is resolved, If you are targeting dual rank DIMMs using address mirroring in hardware, please open a Service Request for assistance.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 63022
日期 01/02/2018
状态 Active
Type 综合文章
器件
IP