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AR# 63640

MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen

描述

Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

When a MIG 7 Series IP core is generated with the "No Buffer" option selected, no create_clock timing constraints are added to the MIG IP XDC constraints file. 

解决方案

When the "No Buffer" option is selected, you must add create_clock constraints for sys_clk and ref_clk in their top-level XDC to ensure that the timing is properly analyzed.

Revision History:
02/19/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 63640
日期 02/20/2015
状态 Active
Type 已知问题
器件
IP
的页面