AR# 63667

UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model

描述

Version Found: DDR4 v7.0

Version Resolved: See (Xilinx Answer 69035)

I am simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, with speed bin=833, and using a Micron memory model.

I am receiving the following error message:

VIOLATION: cmdWR BG:0 B:0 A:0 (BL:8 WL:11 RL:11) @4299688 Required: tRCD-AL - 1 clocks.

解决方案

This violation occurs because of an issue with the Micron memory model using the wrong speed bin parameters.

Please use the most up to date memory model from Micron to resolve the issue.

Revision History:

04/01/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 63667
日期 01/02/2018
状态 Active
Type 已知问题
器件
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IP