AR# 63687

MIG UltraScale RLDRAM3 - IDELAY taps do not move during QVLD Calibration which can cause data errors in hardware


Version Found: MIG UltraScale v6.1

Version Resolved: See (Xilinx Answer 58435)

During calibration, delays are added to DQ and QK signals which can move these signals away from their corresponding QVLD position.

Therefore, QVLD calibration is required to adjust the QVLD signals accordingly by incrementing or decrementing the IDELAY taps.

For MIG UltraScale RLDRAM3 designs, the IDELAY taps do not move which can cause data errors in hardware.

To determine if this is the root cause of data errors seen in your system, check that all of the "user_rd_valid" bits assert on the same clock cycle when 4 commands (BL2) or 2 command (BL4) are sent on the same "user_cmd" bus.


To fix the issue, the following code changes inside are required.

Open and find each instance of "qvld", then change the riu_addr_cal value based on the table below:

if value equal to change to
6'h0b 6'h12
6'h0c 6'h13
6'h0d 6'h14
6'h0e 6'h15
6'h0f 6'h16
6'h10 6'h17
6'h11 6'h18

For example:

28'h0004800: begin //c0_rld3_qvld[0] IO_T1U_N12_45
   riu_addr_cal = 6'h11;
   riu_nibble = 'hb;

This needs to be changed to:

28'h0004800: begin //c0_rld3_qvld[0] IO_T1U_N12_45
   riu_addr_cal = 6'h18;
   riu_nibble = 'hb;

Revision History:

02/24/2015 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A
AR# 63687
日期 01/11/2018
状态 Active
Type 已知问题